Method and system of communicating between peer processors in SoC environment

Patent metadata

Field	Value
Publication number	US-9367493-B2
Application number	US-27509105-A
Country	US
Kind code	B2
Filing date	Dec 9, 2005
Priority date	Dec 9, 2005
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A method and system comprises transferring data from a first processor to at least one pulse generator directly connected to an interrupt control of at least a second processor. The transferring of the data bypasses memory. The method further includes reading the transferred data directly from the at least one pulse generator by the at least a second processor.

First claim

The invention claimed is:

1. A method comprising:
transferring data from a first processor to at least one a single pulse generator directly connected to an interrupt control of at least a second processor, the transferring of the data bypasses memory;
reading the transferred data directly from the at least one single pulse generator by the at least a second processor,
wherein the first processor, the at least one single pulse generator, and the at least a second processor are directly connected to one of an on-chip bus arbiter and an on-chip crossbar/switch, and the single pulse generator is directly connected to the first processor and the at least a second processor; and
partitioning the single pulse generator such that each partition is dedicated to a different processor, of the first processor and the at least a second processor.

2. The method of claim 1 , wherein the transferring of the data and reading of the transferred data is in real-time in a multiprocessor SoC design.

3. The method of claim 1 , wherein the transferring step is provided in a single clock cycle.

4. The method of claim 1 , wherein the reading step is provided in a single clock cycle.

5. The method of claim 1 , further comprising providing write access directly to the at least one single pulse generator.

6. The method of claim 1 , wherein the transferring data includes sending interrupts to the first processor or at least a second processor through the at least one single pulse generator.

7. The method of claim 1 , further comprising obtaining authorization from an arbiter to begin the transferring of data.

8. The method of claim 1 , wherein the reading of the transferred data is directly from the at least one single pulse generator.

9. The method of claim 1 , wherein the transferring of the data and reading of the transferred data is at least (i) processor to processor data traffic, (ii) processor to enabled interrupt device data traffic and (iii) processor to non-enable interrupt devices data.

10. The method of claim 1 , further comprising partitioning the at least one single pulse generator such that each partition is dedicated to at least one of separate functions and separate processors.

11. The method of claim 1 , further comprising fabricating an integrated circuit chip using the method of claim 1 .

12. The method of claim 11 , further comprising distributing the integrated circuit chip.

13. A system, comprising:
at least two processors connected to a bus system; and
at least one pulse generator connected to the bus system and each of the at least two processors, wherein the at least one pulse generator is a write-only device receiving data from the at least two processors which has bypassed memory, and the at least two processors read data directly from the at least one pulse generator, bypassing the memory,
wherein the at least one pulse generator is a single pulse generator directly connected to the at least two processors, wherein the single pulse generator is partitioned such that each partition is dedicated to a different processor, of the at least two processors.

14. The system of claim 13 , wherein the at least one pulse generator is equal to an amount of the at least two processors.

15. The system of claim 13 , wherein the at least one pulse generator is equal to or less than the number of the at least two processors and equal to or greater than 1.

16. The system of claim 13 , wherein the bus system is an on-chip bus arbiter or an on-chip crossbar/switch.

17. The system of claim 13 , wherein the at least one pulse generator is connected directly to an interrupt controller of each of the at least two processors.

18. The system of claim 13 , further comprising at least one interrupt enabled device and one non-interrupt enabled device which write data directly to the at least one pulse generator.

19. The system of claim 13 , wherein the at least one pulse generator is partitioned for at least one of each of the at least two processors, functions and a combination thereof.

20. A system, comprising:
peer processors connected to a bus system; and
a single pulse generator receiving data over the bus system and connected to an interrupt control of the peer processors such that data from one of the peer processors is read directly from the single pulse generator by the one of the peer processors or another of the peer processors,
wherein the peer processors and the single pulse generator are directly connected to one of an on-chip bus arbiter and an on-chip crossbar/switch, the single pulse generator is directly connected to the peer processors, and the single pulse generator is partitioned such that each partition is dedicated to a different processor of the peer processors.

21. The system of claim 20 , wherein the at least one pulse generator is a write-only device receiving data from the one of the peer processors.

22. The system of claim 20 , wherein the at least one single pulse generator bypasses memory such that the one or the another of the peer processors read data directly from the at least one single pulse generator, bypassing the memory.

23. The system of claim 20 , wherein the bus system is an on-chip bus arbiter or an on-chip crossbar/switch.

24. A computer program product comprising a non-transitory storage medium having readable program code embodied in the non-transitory storage medium, the computer program product includes at least one component when executed on a first processor causes the first processor to:
provide a signal in one clock cycle to a single pulse generator, the signal having data associated therewith; and
have a second processor read the data directly from the pulse generator in one clock cycle and bypassing memory,
wherein the first processor, the single pulse generator, and the second processor are directly connected to one of an on-chip bus arbiter and an on-chip crossbar/switch, the single pulse generator is directly connected to the first processor and the second processor, and the single pulse generator is partitioned such that each partition is dedicated to a different processor, of the first processor and the second processor.

25. A system, comprising:
at least two processors connected to a bus system; and
at least one a single pulse generator connected to the bus system and directly connected to each of the at least two processors, wherein the at least one single pulse generator is a write-only device receiving data from the at least two processors which has bypassed memory, and the at least two processors read data directly from the at least one single pulse generator, bypassing the memory,
wherein the at least two processors and the at least one single pulse generator are directly connected to one of an on-chip bus arbiter and an on-chip crossbar/switch, and the single pulse generator is partitioned such that each partition is dedicated to a different processor of the at least two processors.

Assignees

• Devins Robert J
• Milton David W
• Nsame Pascal A
• Globalfoundries Inc

Inventors

• Devins Robert J
• Milton David W
• Nsame Pascal A

Classifications

• G06F15/17

  using an input/output type connection, e.g. channel, I/O port · CPC title

• G06F13/24 Primary

  using interrupt (G06F13/32 takes precedence) · CPC title