Instruction and logic for support of code modification in translation lookaside buffers

Patent metadata

Field	Value
Publication number	US-9367477-B2
Application number	US-201414494781-A
Country	US
Kind code	B2
Filing date	Sep 24, 2014
Priority date	Sep 24, 2014
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory location. The processor further includes a translation lookaside buffer including logic to store translation indicators from a physical map. Each translation indicator indicates whether a corresponding memory location includes translated code to be protected. The processor further includes a translation indicator agent including logic to determine whether the buffer indicates whether the memory location has been modified subsequent to translation of the instruction.

First claim

What is claimed is:

1. A processor, comprising:
a processor core including a first logic to execute a translated instruction, the translated instruction translated from an instruction stored in a memory location;
a translation lookaside buffer (TLB) including a second logic to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; and
a translation indicator agent (XTBA) including a third logic to determine whether the TLB indicates whether the memory location has been modified subsequent to translation of the instruction.

2. The processor of claim 1 , further comprising a page miss handler including a fourth logic to issue a virtual-to-physical translation, the translation generating an update to the translation indicators of the TLB.

3. The processor of claim 2 , wherein the page miss handler further includes a fifth logic to issue the virtual-to-physical translation upon a determination by the XTBA that the TLB indicates that the memory location has been modified subsequent to translation of the instruction.

4. The processor of claim 2 , wherein the TLB further includes a fifth logic to determine the translation indicators from the physical map upon completion of a page walk of an access to physical memory.

5. The processor of claim 2 , wherein the page miss handler further includes:
a fifth logic to assemble the translation indicators into a vector; and
a sixth logic to place the vector into the TLB.

6. The processor of claim 1 , further comprising an input-output engine including:
a fourth logic to determine a direct memory access to the physical map; and
a fifth logic to update the TLB based upon the determined direct memory access.

7. The processor of claim 5 , wherein the input-output engine further includes a sixth logic to update the TLB upon completion of a last-level page walk of an access to physical memory.

8. A method comprising, within a processor:
executing a translated instruction, the translated instruction translated from an instruction stored in a memory location;
storing translation indicators from a physical map into a translation lookaside buffer (TLB), each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; and
determining whether the TLB indicates whether the memory location has been modified subsequent to translation of the instruction.

9. The method of claim 8 , further comprising issuing a virtual-to-physical translation to generate an update to the translation indicators of the TLB.

10. The method of claim 9 , further comprising issuing the virtual-to-physical translation upon a determination that the TLB indicates that the memory location has been modified subsequent to translation of the instruction.

11. The method of claim 9 , further comprising determining the translation indicators from the physical map upon completion of a page walk of an access to physical memory.

12. The method of claim 8 , further comprising:
determining a direct memory access to the physical map; and
updating the TLB based upon the determined direct memory access.

13. The method of claim 12 , further comprising updating the TLB upon completion of a last-level page walk of an access to physical memory.

14. A system comprising:
a processor core including a first logic to execute a translated instruction, the translated instruction translated from an instruction stored in a memory location;
a translation lookaside buffer (TLB) including a second logic to store translation indicators from a physical map, each translation indicator to indicate whether a corresponding memory location includes translated code to be protected; and
a translation indicator agent (XTBA) including a third logic to determine whether the TLB indicates whether the memory location has been modified subsequent to translation of the instruction.

15. The system of claim 14 , further comprising a page miss handler including a fourth logic to issue a virtual-to-physical translation generating an update to the translation indicators of the TLB.

16. The system of claim 15 , wherein the page miss handler further includes a fifth logic to issue the virtual-to-physical translation upon a determination by the XTBA that the TLB indicates that the memory location has been modified subsequent to translation of the instruction.

17. The system of claim 15 , wherein the TLB further includes a fifth logic to determine the translation indicators from the physical map upon completion of a page walk of an access to physical memory.

18. The system of claim 15 , wherein the page miss handler further includes:
a fifth logic to assemble the translation indicators into a vector; and
a sixth logic to place the vector into the TLB.

19. The system of claim 14 , further comprising an input-output engine including:
a fourth logic to determine a direct memory access to the physical map; and
a fifth logic to update the TLB based upon the determined direct memory access.

20. The system of claim 19 , wherein the input-output engine further includes a sixth logic to update the TLB upon completion of a last-level page walk of an access to physical memory.

Assignees

• Intel Corp

Inventors

• Topp Jaroslaw
• Cooray Niranjan L
• Latorre Fernando

Classifications

• G06F2212/30

  Providing cache or TLB in specific location of a processing system · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/68

  Details of translation look-aside buffer [TLB] · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F9/30003

  Arrangements for executing specific machine instructions · CPC title