Address Range Based Memory Hints for Prefetcher, Cache and Memory Controller
US-2024385966-A1 · Nov 21, 2024 · US
Memory management apparatus, method, and system
US9367476B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9367476-B2 |
| Application number | US-201314047579-A |
| Country | US |
| Kind code | B2 |
| Filing date | Oct 7, 2013 |
| Priority date | Nov 30, 2012 |
| Publication date | Jun 14, 2016 |
| Grant date | Jun 14, 2016 |
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Abstract
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The present invention discloses a memory management apparatus, method, and system. An OS-based memory management apparatus associated with main memory includes a memory allocation controller configured to control a first memory region within the main memory such that the first memory region is used as a buffer cache depending on whether an input/output device is active or not in order to use the first memory region, allowing memory reservation for the input/output device, in the OS. The memory allocation controller controls the first memory region such that the first memory region is used as an eviction-based cache.
First claim
Opening claim text (preview).
What is claimed is: 1. An OS-based memory management apparatus associated with main memory, comprising: a memory allocation controller configured to control a first memory region within the main memory such that the first memory region, comprising reservation memory for an input/output device among input/output devices, is used as a buffer cache when the input/output device is not active; and a first buffer cache within the OS, wherein: the memory allocation controller contro…
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- G06F12/0897Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
- G06F12/06Primary
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US9367476B2 cover?
- The present invention discloses a memory management apparatus, method, and system. An OS-based memory management apparatus associated with main memory includes a memory allocation controller configured to control a first memory region within the main memory such that the first memory region is used as a buffer cache depending on whether an input/output device is active or not in order to use th…
- Who is the assignee on this patent?
- Univ Sungkyunkwan Res & Bus
- What technology area does this patent fall under?
- Primary CPC classification G06F12/0897. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).