Method and system for improving memory access performance

US9367465B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9367465-B2
Application numberUS-10179208-A
CountryUS
Kind codeB2
Filing dateApr 11, 2008
Priority dateApr 12, 2007
Publication dateJun 14, 2016
Grant dateJun 14, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention relates to a computing system which includes a processor and a memory. It also includes a memory access optimizer which is arranged to affect memory access of a program during runtime execution of the software. The program includes a plurality of application elements, each comprising a text field containing a text section, and a memory access field. The memory access optimizer is arranged to implement memory access data in the memory access field in order to affect memory access of the application element. The text section is unchanged by the memory access data implementation.

First claim

Opening claim text (preview).

What is claimed is: 1. A computing system comprising: a processor; a memory; a memory access optimizer configured to affect memory access of a program during runtime execution of the program; the program including a plurality of application elements comprising a text field containing a text section, and a memory access field, the memory access optimizer configured to implement memory access data in the memory access field in order to affect memory access of the application element, whereby the memory access optimizer is configured to prevent change to the text section by the memory access data implementation. 2. A computing system in accordance with claim 1 , wherein, the memory access data is arranged to control a prefetch instruction for affecting a prefetch of data from memory. 3. A computing system in accordance with claim 1 , wherein the memory access data is arranged to control selection of a program routine for execution. 4. A computing system in accordance with claim 1 , further comprising: a compiler arranged to implement memory access options within a program including a plurality of application elements, the memory access options being arranged to affect memory access patterns of the program during runtime, and the compiler being arranged to provide a memory access field in the application elements, wherein the value of a datum in the memory access field is arranged to implement the memory access options. 5. A computing system in accordance with claim 4 , wherein the memory access options include an instruction for causing prefetch of data from memory. 6. A computing system in accordance with claim 4 , wherein the memory access options include an instruction for selection of a program routine. 7. A method of compiling a computer program, wherein a computer has instructions stored in non-transitory memory executable by a processor and the computer program includes a plurality of application elements comprising a text field containing a text section, the method comprising: writing memory access options into the application elements for affecting memory access patterns of the computer program during runtime providing a memory access field for the application element(s), wherein the value of a datum in the memory access field is arranged to implement memory access options; and implementing memory access in the memory access field in order to affect memory access of the application elements, wherein implementing the memory access in the memory access field is performed in a manner to prevent change to the text section while implementing memory access in the memory access field. 8. A method in accordance with claim 7 , wherein the memory access options include instructions for causing a prefetch of data from memory. 9. A method in accordance with claim 7 , wherein the memory access options include an instruction for selection of a program routine. 10. A computing device, including instruction stored in non-transitory memory and executed by a processor to control compiling of a program the program having a plurality of application elements including a text field and a text section, where the instructions are executed to: write memory access options into the application elements for affecting memory access patterns of the computer program during runtime; provide a memory access field for the application element(s), wherein a value of a datum in the memory access field is configured to implement memory access options; and implement memory access in the memory access field in order to affect memory access of the application elements, wherein implementing the memory access in the memory access field is performed in a manner to prevent change to the text section while implementing memory access in the memory access field.

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What does patent US9367465B2 cover?
The present invention relates to a computing system which includes a processor and a memory. It also includes a memory access optimizer which is arranged to affect memory access of a program during runtime execution of the software. The program includes a plurality of application elements, each comprising a text field containing a text section, and a memory access field. The memory access optim…
Who is the assignee on this patent?
Saraswati Sujoy, Hewlett Packard Entpr Dev Lp
What technology area does this patent fall under?
Primary CPC classification G06F12/0862. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).