Semiconductor integrated circuit and drive apparatus including the same

Patent metadata

Field	Value
Publication number	US-9367386-B2
Application number	US-201414330797-A
Country	US
Kind code	B2
Filing date	Jul 14, 2014
Priority date	Aug 31, 2011
Publication date	Jun 14, 2016
Grant date	Jun 14, 2016

Abstract

A semiconductor integrated circuit includes a first transmission circuit generating and outputting a first transmission signal reflecting a first data signal supplied from outside, a first reception circuit reproducing the first data signal based on a first reception signal, a first isolation element isolating the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal, a second transmission circuit generating and outputting a second transmission signal reflecting a second data signal supplied from outside, a second reception circuit reproducing the second data signal based on a second reception signal, a second isolation element isolating the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal, and a third transmission circuit generating and outputting a third transmission signal reflecting the second data signal.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a first transmission circuit generating and outputting a first transmission signal reflecting a first data signal supplied from outside;
a first reception circuit reproducing the first data signal based on a first reception signal;
a first isolation element isolating the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal;
a second transmission circuit generating and outputting a second transmission signal reflecting a second data signal supplied from outside;
a second reception circuit reproducing the second data signal based on a second reception signal;
a second isolation element isolating the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal;
a third transmission circuit generating and outputting a third transmission signal reflecting the second data signal;
a third reception circuit reproducing the second data signal based on a third reception signal;
a third isolation element isolating the third transmission circuit from the third reception circuit and transmitting the third transmission signal as the third reception signal;
a control part which outputs a stop signal regardless of the first data signal supplied from outside to the first transmission circuit when the control part decides that both the first data signal reproduced by the first reception circuit and the second data signal reproduced by the third reception circuit are the same logical level signals;
a first gate driver outputting a first gate control signal based on the first data signal reproduced by the first reception circuit; and
a second gate driver outputting a second gate control signal based on the second data signal reproduced by the second reception circuit and the second gate control signal being used to control on/off operations of an output transistor for controlling a current flowing through a load.

2. The semiconductor integrated circuit according to claim 1 ,
wherein, upon detection of an abnormality, the control part turns off the output transistor by outputting the stop signal.

3. The semiconductor integrated circuit according to claim 1 , wherein the first, the second and the third isolation elements are comprised of a transformer.

4. The semiconductor integrated circuit according to claim 1 , wherein the first, the second and the third isolation elements are comprised of a GMR (Giant Magneto Resistive) element isolator.

5. The semiconductor integrated circuit according to claim 1 , wherein the first, the second and the third isolation elements are comprised of a capacitor.

6. The semiconductor integrated circuit according to claim 1 , wherein the first, the second and the third isolation elements are comprised of a photo-coupler.

7. The semiconductor integrated circuit according to claim 1 , wherein the first and the second transmission circuits are mounted over a first semiconductor chip driven by a first power source,
wherein the first and the third reception circuits are mounted over a second semiconductor chip driven by a second power source,
wherein the second reception circuit and the third transmission circuit are mounted over a third semiconductor chip driven by a third power source and
wherein the control part is mounted over the second semiconductor chip along with the first and the third reception circuit.

8. The semiconductor integrated circuit according to claim 1 , wherein, upon detection of an abnormality, the control part turns off an output transistor by outputting the stop signal.

9. The semiconductor integrated circuit according to claim 1 , wherein upon detection of an abnormality, the control part outputs a stop signal regardless of the first data signal supplied from outside to the first transmission circuit when the control part decides that both the first data signal reproduced by the first reception circuit and the second data signal reproduced by the third reception circuit are the same logical level signals.

10. A method of semiconductor integrated circuit, the method comprising:
generating and outputting, by a first transmission circuit, a first transmission signal reflecting a first data signal supplied from outside;
reproducing, by a first reception circuit, the first data signal based on a first reception signal;
isolating, by a first isolation element, the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal;
generating and outputting, by a second transmission circuit, a second transmission signal reflecting a second data signal supplied from outside;
reproducing, by a second reception circuit, the second data signal based on a second reception signal;
isolating, by a second isolation element, the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal;
generating and outputting, by a third transmission circuit, a third transmission signal reflecting the second data signal;
reproducing, by a third reception circuit, the second data signal based on a third reception signal;
isolating, by a third isolation element, the third transmission circuit from the third reception circuit and transmitting the third transmission signal as the third reception signal;
outputting, by a control part, a stop signal regardless of the first data signal supplied from outside to the first transmission circuit when the control part decides that both the first data signal reproduced by the first reception circuit and the second data signal reproduced by the third reception circuit are the same logical level signals;
outputting, by a first gate driver, a first gate control signal based on the first data signal reproduced by the first reception circuit; and
outputting, by a second gate driver, a second gate control signal based on the second data signal reproduced by the second reception circuit and the second gate control signal being used to control on/off operations of an output transistor for controlling a current flowing through a load.

11. The method according to claim 10 ,
wherein, upon detection of an abnormality, the control part turns off the output transistor by outputting the stop signal.

12. The method according to claim 10 , wherein, upon detection of an abnormality, the control part turns off an output transistor by outputting the stop signal.

13. The method according to claim 10 , wherein upon detection of an abnormality, the control part outputs a stop signal regardless of the first data signal supplied from outside to the first transmission circuit when the control part decides that both the first data signal reproduced by the first reception circuit and the second data signal reproduced by the third reception circuit are the same logical level signals.

14. The method according to claim 10 , wherein the first, the second and the third isolation elements are comprised of at least one of a transformer, a GMR (Giant Magneto Resistive) element isolator, a capacitor, and a photo-coupler.

15. The method according to claim 10 , wherein the first and the second transmission circuits are mounted over a first semiconductor chip driven by a first power source,
wherein the first and the third reception circuits are mounted over a second semiconductor chip driven by a second power source,
wherein the second reception circuit and the third transmission circuit are mounted over a

Assignees

• Renesas Electronics Corp

Inventors

• Kaeriyama Shunichi

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5445

  being orthogonal to a side surface of the chip, e.g. parallel arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title