Self-calibration temperature control device and method

US9366583B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9366583-B2
Application numberUS-201214398116-A
CountryUS
Kind codeB2
Filing dateJun 19, 2012
Priority dateJun 13, 2012
Publication dateJun 14, 2016
Grant dateJun 14, 2016

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A self-calibration temperature control method and device includes a temperature feedback and control unit, a precise temperature measurement unit, and a temperature calibration unit. The temperature feedback and control unit has a negative temperature coefficient thermistor and an analog feedback control circuit that are connected with a controlled heating element. The temperature calibration unit includes a CPU, a data latch circuit with an input end connected with the CPU through a bus, and a digital potentiometer connected with the temperature feedback and control unit, an output end of the data latch circuit being connected with the digital potentiometer through the bus. The CPU includes a judging unit, a calibration parameter storage module, and a digital potentiometer connection step setting module configured to determine an updated calibration parameter value according to historic calibration parameter data, and further to adjust a step value according to a preset resistance value, thereby adjusting a resistance value of the digital potentiometer.

First claim

Opening claim text (preview).

The invention claimed is: 1. A self-calibration temperature control device, mainly comprising: a temperature feedback and control unit connected with a controlled heating element to control the work state thereof, a precise temperature measurement unit connected with the controlled heating element to measure a stable temperature thereof, and a temperature calibration unit connected with the precise temperature measurement unit and the temperature feedback and control unit; wherein the temperature calibration unit is configured for obtaining temperature from the precise temperature measurement unit, dynamically calibrating temperature drift, and inputting the calibrated result into the temperature control and feedback unit; wherein the temperature feedback and control unit comprises: a negative temperature coefficient thermistor and an analog feedback control circuit that are connected with the controlled heating element to control the final stable temperature of the controlled heating element reaching the setting value through the analog feedback control circuit; wherein the temperature calibration unit comprises: a CPU with a preset temperature range value and a preset resistance adjustment step value, being connected with the precise temperature measurement unit, a data latch circuit with an input end connected with the CPU through a bus, and a digital potentiometer connected with the temperature feedback and control unit, and an output end of the data latch circuit is connected with the digital potentiometer through the bus; wherein the CPU comprises: a judging unit configured for judging whether the temperature value measured by the precise temperature measurement unit is within a preset range, a calibration parameter storage module configured for storing historical calibration parameter data, and a digital potentiometer connection step setting module, the digital potentiometer connection step setting module being configured to determine an updated calibration parameter value according to the historic calibration parameter data, and further to adjust a step value according to a preset resistance value. 2. The self-calibration temperature control device according to claim 1 , wherein the temperature feedback and control unit comprises an NTC thermistor, a precise setting resistor, a voltage reference circuit, a ½ voltage division circuit, a first buffer circuit, a second buffer circuit, an integrating circuit, an inverse proportional amplifier circuit, a voltage summing circuit, a level mapping circuit and a DC/DC module circuit, wherein: one end of the NTC thermistor is grounded and the other end of the NTC thermistor is connected with the precise setting resistor and further connected with a non-inverting input end of the first buffer circuit; one end of the precise temperature setting resistor is connected with an NTC resistor, and further connected with the non-inverting input end of the first buffer circuit, and the other end of the precise temperature setting resistor is connected with the digital potentiometer; the output voltage of the voltage reference circuit is connected with the digital potentiometer and the output voltage thereof is further connected with a first resistor of the ½ voltage division circuit; the ½ voltage division circuit comprises the first resistor, a second resistor and a first operational amplifier; the first resistor is connected with the output of the voltage reference circuit and the other end of the first resistor is connected with the second resistor and is further connected with the non-inverting end of the first operational amplifier; the first operational amplifier is connected into a voltage follower way, the inverting end of the first operational amplifier is connected with the output end, the output end of the first operational amplifier is connected with the non-inverting end of a third operational amplifier, and the output end of the first operational amplifier is further connected with the non-inverting end of a fourth operational amplifier; the first buffer circuit is structured by the voltage follower which is connected by a second operational amplifier; the second buffer circuit is structured by the voltage follower which is connected by the first operational amplifier; the non-inverting input end of the first operational amplifier is connected with the first resistor of the ½ voltage division circuit, the inverting end of the first operational amplifier is connected with the output end of the first operational amplifier, and the output end operating and amplifying the first operational amplifier is connected with the non-inverting end of the third operational amplifier which is operated and amplified by the integrator, and the output end operating and amplifying the first operational amplifier is further connected with the non-inverting end of the fourth operational amplifier which is operated and amplified by the inverse proportional amplifier circuit; the integrating circuit comprises a fifth resistor, a third operational amplifier and a feedback capacitor; one end of the fifth resistor is connected with the buffer output end and is further connected with the third resistor, the other end of the fifth resistor is connected with the inverting input end of the third operational amplifier and is further connected with one end of the feedback capacitor, one end of the feedback capacitor is connected with the inverting end of the third operational amplifier, and the other end of the feedback capacitor is connected with the output end which operates and amplifies the third operational amplifier; the output of the third operational amplifier is connected with a sixth resistor of the voltage summing circuit and the non-inverting end of the third operational amplifier is connected with the output end of the first operational amplifier in the buffer circuit; the reverse proportion amplifier circuit comprises a fourth operational amplifier, a third resistor and a fourth resistor, the non-inverting end of the fourth operational amplifier is connected with the output end of the first operational amplifier, the inverting end of the fourth operational amplifier is connected with a common node formed by the third and fourth resistors, the other end of the third resistor is connected with the output of the second operational amplifier and is further connected with one end of the fifth resistor, one end of the fourth resistor is connected with the inverting end of the fourth operational amplifier and is further connected with the third resistor, and the other end of the fourth resistor is connected with the output of the fourth operational amplifier; the voltage summing circuit consists of two equivalent sixth and seventh resistors, one end of the sixth resistor is connected with the output of the integrator, and the other end of the sixth resistor is connected with the seventh resistor, one end of the seventh resistor is connected with the output of the reserve proportion amplifier circuit, and the other end of the seventh resistor is connected with the sixth resistor; the common node formed by the seventh resistor and the sixth resistor is connected with the input end of the level mapping circuit; the level mapping circuit consists of a first voltage follower, a second voltage follower, an eighth resistor and a ninth resistor, the non-inverting end of the first voltage follower is connected with the common node formed by the sixth resistor and the seventh resistor of the voltage summing circuit, the inverting end of the first voltage follower is connected with the output, the output of the first voltage follower is further connected with one end of the eighth resistor, the other end of the eighth resistor is connected with a common node formed by the ninth resistor, this common node is connected with the non-inverting end of the secon

Assignees

Inventors

Classifications

  • the element being a non-linear resistance, e.g. thermistor (G01K7/26 takes precedence) · CPC title

  • G01K15/005Primary

    Calibration · CPC title

  • Control of temperature · CPC title

  • using digital means · CPC title

  • the sensing element having a resistance varying with temperature, e.g. a thermistor · CPC title

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What does patent US9366583B2 cover?
A self-calibration temperature control method and device includes a temperature feedback and control unit, a precise temperature measurement unit, and a temperature calibration unit. The temperature feedback and control unit has a negative temperature coefficient thermistor and an analog feedback control circuit that are connected with a controlled heating element. The temperature calibration u…
Who is the assignee on this patent?
Xiang Xiaofei, Zhao Zhixiang, Chai Shaoguo, and 1 more
What technology area does this patent fall under?
Primary CPC classification G01K15/005. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 14 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).