Accelerator circuit and image processing apparatus

Patent metadata

Field	Value
Publication number	US-9363412-B2
Application number	US-201514681290-A
Country	US
Kind code	B2
Filing date	Apr 8, 2015
Priority date	Apr 18, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

An accelerator circuit for an image processing apparatus includes a buffer circuit that temporarily stores image data obtained from N (N>1) data sources and an arithmetic circuit that performs a predetermined arithmetic operation on pixel data. The buffer circuit includes N buffer memories and N 2D registers associated with the respective N data sources, a control circuit, and a selector. Each buffer memory temporarily stores image data obtained from a corresponding one of the N data sources. Each 2D register temporarily stores pixel data, which is a part of image data stored in a corresponding one of the N buffer memories, of an area of a predetermined size. The selector is controlled by the control circuit so as to select, when pixel data is stored in one of the N 2D registers, the pixel data and send the pixel data to the arithmetic circuit.

First claim

What is claimed is:

1. An accelerator circuit for an image processing apparatus, the accelerator circuit comprising:
a buffer circuit configured to obtain image data from N data sources and temporarily store the image data, N being a number greater than one; and
an arithmetic circuit;
the buffer circuit including
N buffer memories and N two-dimensional (2D) registers corresponding, respectively, to the N data sources,
a control circuit, and
a selector, wherein

each of the N buffer memories is configured to temporarily store image data obtained from a corresponding one of the N data sources,
each of the N 2D registers is configured to temporarily store pixel data that is of an area of a first size and is a part of image data stored in a corresponding one of the N buffer memories,
the selector is configured to select pixel data of the first size stored in one of the N 2D registers and send the selected pixel data to the arithmetic circuit under control of the control circuit,
the arithmetic unit is configured to perform a first arithmetic operation on the selected pixel data of the first size, and
the control circuit is configured to control the selector to perform the sending when pixel data is stored in one of the N 2D registers.

2. The accelerator circuit according to claim 1 , wherein each of the N buffer memories includes line memories a number of which is equal to or smaller than a number of rows in a 2D register from among the N 2D registers.

3. An accelerator circuit for an image processing apparatus, the accelerator circuit comprising:
a buffer circuit configured to obtain image data from N data sources and temporarily store the image data, N being a number greater than one;
an arithmetic circuit;
the buffer circuit including
N buffer memories corresponding, respectively, to the N data sources,
a control circuit, and
a selector, wherein

each of the N buffer memories is configured to temporarily store image data obtained from a corresponding one of the N data sources,
the selector is configured to select image data stored in one of the N buffer memories and send the selected image data to the arithmetic circuit under control of the control circuit,
the arithmetic unit is configured to perform a first arithmetic operation on pixel data of a first size, the pixel data being part of the selected image data,
the arithmetic circuit includes a two-dimensional (2D) register that is configured to temporarily stores pixel data of the first size, and
the control circuit is configured to control the selector to perform the sending when pixel data is stored in one of the N buffer memories.

4. The accelerator circuit according to claim 3 , wherein each of the N buffer memories includes line memories a number of which is equal to or smaller than a number of rows in the 2D register.

5. An image processing apparatus comprising:
a processor;
a main memory;
the accelerator circuit according to claim 1 ;
an image input circuit configured to feed image data obtained from an entity external to the image processing apparatus to the accelerator circuit as first image data; and
a DMA control circuit configured to transfer image data in the main memory to the accelerator circuit as second image data.

6. An accelerator circuit for an image processing apparatus, the accelerator circuit comprising:
a buffer circuit configured to obtain image data from N data sources and temporarily store the image data, N being a number greater than one;
an arithmetic circuit;
the buffer circuit including
a plurality of buffer memories, the plurality of buffer memories including at least N buffer memories that correspond, respectively, to the N data sources, and
a selector, wherein

each of the N buffer memories is configured to temporarily store image data obtained from a corresponding one of the N data sources,
the selector is configured to select image data that has been stored in one of the N buffer memories and send the selected image data to the arithmetic circuit, and
the arithmetic unit is configured to perform a first arithmetic operation on pixel data of a first size, the pixel data being part of the selected image data.

7. The accelerator circuit of claim 6 , wherein,
the buffer circuit further includes a plurality of two-dimensional (2D) registers, the plurality of 2D registers including at least N 2D registers that correspond, respectively, to the N buffer memories,
the N 2D registers are each configured to receive the image data temporarily stored in corresponding buffer memories, from among the N buffer memories, and
the selector is configured such that the selected image data selected by the selector is image data stored in one of the N 2D registers.

8. The accelerator circuit of claim 7 , further comprising:
a control circuit;
the control circuit being configured to control the selector to perform the sending when pixel data is stored in one of the N 2D registers.

9. The accelerator circuit of claim 6 , wherein the arithmetic circuit includes a two-dimensional (2D) register that is configured to temporarily store pixel data of the first size.

10. The accelerator circuit of claim 9 , further comprising:
a control circuit;
the control circuit being configured to control the selector to perform the sending when pixel data is stored in one of the N buffer memories.

Assignees

• Sugimoto Hideki
• Matsuoka Akihiro
• Sonoda Shimpei
• Ricoh Co Ltd

Inventors

• Sugimoto Hideki
• Matsuoka Akihiro
• Sonoda Shimpei

Classifications

• H04N1/32561 Primary

  using a programmed control device, e.g. a microprocessor · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title