Ultra low power-data driven networking processing device for avoiding overload

US9363196B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9363196-B2
Application numberUS-201214232951-A
CountryUS
Kind codeB2
Filing dateJul 9, 2012
Priority dateJul 15, 2011
Publication dateJun 7, 2016
Grant dateJun 7, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention is provided with: a data-driven processor comprising at least a firing control which determines whether or not firing conditions have been met by determining whether or not all packets necessary for instruction execution have been received when a packet that convey a part of partitioned data to be processed has been input, and a data processing unit for performing processing corresponding to the packets transmitted from the firing control if the firing conditions have been met; a power supply circuit for supplying power to the data-driven processor; and overload avoidance means for refusing input of the packets to the data-driven processor, if a determination has been made that a data processing load in the data-driven processor may reach an overloaded state in which the data processing may stall, on the basis of current consumption in the data-driven processor. Accordingly, power consumption in a networking system is reduced.

First claim

Opening claim text (preview).

The invention claimed is: 1. An ultra-low-power data-driven networking processing device for avoiding overload, comprising: a data-driven processor including at least a firing control device for determining whether firing conditions have been satisfied by determining whether all packets required to execute an instruction have been received, with respect to packets that convey partitioned data to be processed, and a data processing device for performing processing based on packets transmitted from the firing control device if the firing conditions have been satisfied; a power circuit for supplying power to the data-driven processor; an interface for denying input of packets to a terminal, if it is determined that a data processing load of the data-driven processor can enter an overload state in which data processing is congested, based on current consumption of the data-driven processor; and a pipeline stage including a first merge device for merging packets to be input to the data-driven processor with data processed by the data processing device, the firing control device for receiving packets or data transmitted from the first merge device, a second merge device for merging data transmitted from the firing control device with data processed by the data processing device, an instruction fetch device for fetching an instruction based on data transmitted from the second merge device, an instruction decode device for interpreting the instruction transmitted from the instruction fetch device, the data processing device for processing the instruction interpreted by the instruction decode device, a memory access device for reading and writing data processed by the data processing device from and to memory, a second branch device for transmitting data to the second merge device if, based on data written by the memory access device, the data corresponds to a unary operation and requires processing again by the data processing device, and for transmitting the data to a downstream first branch device if the data corresponds to a multi-input operation and does not require data processing by the data processing device, and the first branch device for transmitting data to the first merge device if, based on the data transmitted from the second branch device, the data requires data processing again by the data processing device, and for outputting the device from the data-driven processor if the data does not require data processing by the data processing device. 2. The ultra-low-power data-driven networking processing device for avoiding overload of claim 1 , further comprising an output control means interface for stopping output of relay packets, if it is determined that the data processing load of the data-driven processor is higher than a preset high-load state, based on the current consumption of the data-driven processor. 3. The ultra-low-power data-driven networking processing device for avoiding overload of claim 1 , further comprising: power circuit for supplying the data-driven processor as a voltage depending on the data processing load of the date-driven processor, based on the current consumption of the data-driven processor. 4. An ultra-low-power data-driven networking processing device for avoiding overload, comprising: a data-driven processor including at least a firing control device for determining whether firing conditions have been satisfied by determining whether all packets required to execute an instruction have been received, with respect to the packets that convey partitioned data to be processed, and a data processing device for performing processing based on packets transmitted from the firing control unit device if the firing conditions have been satisfied; galvanometer for detecting current consumption of the data-driven processor; power circuit for supplying the data-driven processor as a voltage depending on a data processing load of the data-driven processor, based on current consumption of the data-driven processor; and a pipeline stage including a first merge device for merging packets to be input to the data-driven processor with data processed by the data processing device, the firing control device for receiving packets or data transmitted from the first merge device, a second merge device for merging data transmitted from the firing control device with data processed by the data processing device, an instruction fetch device for fetching an instruction based on data transmitted from the second merge device, an instruction decode device for interpreting the instruction transmitted from the instruction fetch device, the data processing device for processing the instruction interpreted by the instruction decode device, a memory access device for reading and writing data processed by the data processing device from and to memory, a second branch device for transmitting data to the second merge device if, based on data written by the memory access device, the data corresponds to a unary operation and requires processing again by the data processing device, and for transmitting the data to a downstream first branch device if the data corresponds to a multi-input operation and does not require data processing by the data processing device, and the first branch device for transmitting data to the first merge device if, based on the data transmitted from the second branch device, the data requires data processing again by the data processing device, and for outputting the data from the data-driven processor if the data does not require data processing by the data processing device. 5. An ultra-low-power data-driven networking processing device for avoiding overload, comprising: a data-driven processor including at least a firing control device for determining whether firing conditions have been satisfied by determining whether all packets that convey partitioned data to be processed have been received, and a data processing device for performing processing based on data transmitted from the firing control device if the firing conditions have been satisfied; and a pipeline stage including a first merge device for merging packets to be input to the data-driven processor with data processed by the data processing device, the firing control device for receiving packets or data transmitted from the first merge device, a second merge device for merging data transmitted from the firing control device with data processed by the data processing device an instruction fetch device for fetching an instruction based on data transmitted from the second merge device, an instruction decode device for interpreting the instruction transmitted from the instruction fetch device the data processing unit device for processing the instruction interpreted by the instruction decode device, a memory access unit device for reading and writing data processed by the data processing unit device from and to memory, a second branch device for transmitting data to the second merge unit device if the data corresponds to a unary operation and requires processing again by the data processing device, based on data written by the memory access device, and for transmitting the data to a downstream first branch device if the data corresponds to a multi-input operation or does not require data processing in the data processing device, and the first branch device for transmitting data to the first merge device if the data requires data processing again by the data processing device, based on the data transmitted from the second branch device, and for outputting the data from the data-driven processor if the data does not require data processing in the data processing device.

Assignees

Inventors

Classifications

  • G06F1/28Primary

    Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

  • H04L47/745Primary

    Reaction in network · CPC title

  • Cross-Sectional Technologies · mapped topic

  • by diverting traffic away from congested entities · CPC title

  • by lowering the supply or operating voltage · CPC title

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Frequently asked questions

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What does patent US9363196B2 cover?
The present invention is provided with: a data-driven processor comprising at least a firing control which determines whether or not firing conditions have been met by determining whether or not all packets necessary for instruction execution have been received when a packet that convey a part of partitioned data to be processed has been input, and a data processing unit for performing processi…
Who is the assignee on this patent?
Nishikawa Hiroaki, Sannomiya Shuji, Iwata Makoto, and 5 more
What technology area does this patent fall under?
Primary CPC classification G06F1/28. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).