Low power squelch circuit

Patent metadata

Field	Value
Publication number	US-9363070-B2
Application number	US-201113994096-A
Country	US
Kind code	B2
Filing date	Dec 21, 2011
Priority date	Dec 21, 2011
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal; and a differential amplifier to amplify the sampled differential signal.

First claim

We claim:

1. An apparatus comprising:
a clock generation unit to generate first and second phases of a clock signal;
a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampling unit to generate a sampled differential signal, the sampling unit comprises:
a first switch to sample a first signal of the differential input signal to generate a first sampled signal of the sampled differential signal, and
a second switch to sample a second signal of the differential input signal to generate a second sampled signal of the sampled differential signal, wherein the first and second switches are operable by the first phase of the clock signal; and

a differential amplifier to amplify the sampled differential signal.

2. An apparatus comprising:
a clock generation unit to generate first and second phases of a clock signal;
a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampling unit to generate a sampled differential signal, the sampling unit comprises:
a first switch to sample a first signal of the differential input signal to generate a first sampled signal of the sampled differential signal,
a second switch to sample a second signal of the differential input signal to generate a second sampled signal of the sampled differential signal, and
a third switch to couple the first signal, of the differential amplified signal, to a node coupled to the second switch; and

a differential amplifier to amplify the sampled differential signal.

3. The apparatus of claim 2 , wherein the sampling unit further comprises:
a fourth switch to couple the second signal, of the differential amplified signal, to a node coupled to the first switch.

4. The apparatus of claim 3 , wherein the third and fourth switches are operable by the second phase of the clock signal.

5. The apparatus of claim 1 , wherein the first switch is coupled to the differential amplifier via a first capacitor.

6. The apparatus of claim 1 , wherein the second switch is coupled to the differential amplifier via a second capacitor.

7. The apparatus of claim 1 further comprises a seventh switch for coupling a ground node with an input of the differential amplifier via a fourth capacitor, wherein the seventh switch is operable by the first phase of the clock signal.

8. The apparatus of claim 7 further comprises an eighth switch for coupling a high power supply node with the input of the differential amplifier via the fourth capacitor, wherein the eighth switch is operable by the second phase of the clock signal.

9. The apparatus of claim 1 , wherein the sampling unit and the differential amplifier are positioned in a receiver which is one of:
a Mobile Industry Processor Interface (MIPI®) M-PHY SM receiver;
a Peripheral Component Interconnect Express (PCIe) receiver;
a Serial Advanced Technology Attachment (SATA) receiver;
a Serial Attached SCSI (SAS) receiver;
a Double Data Rate x (DDRx) receiver, were ‘x’ is an integer;
a High-Definition Multimedia Interface (HDMI) receiver; or
a Universal Serial Bus x (USBx) receiver, where ‘x’ is an integer.

10. The apparatus of claim 9 , wherein the MIPI® M-PHY SM receiver is operable to receive high-speed (HS) GEAR rate signals.

11. The apparatus of claim 1 , wherein the differential amplifier is operable to reject common mode in the sampled differential signal.

12. The apparatus of claim 1 , wherein the differential amplifier has a built-in auto-zero function.

13. The apparatus of claim 1 , wherein the differential amplifier is operable to amplify independent of offset cancellation in the sampled differential signal.

14. An apparatus comprising:
a clock generation unit to generate first and second phases of a clock signal;
a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampling unit to generate a sampled differential signal;
a differential amplifier to amplify the sampled differential signal; and
a first switch for coupling a ground node with an input of the differential amplifier via a third capacitor, wherein the first switch is operable by the first phase of the clock signal.

15. The apparatus of claim 14 further comprises a second switch for coupling a high power supply node with the input of the differential amplifier via the third capacitor, wherein the second switch is operable by the second phase of the clock signal.

16. An apparatus comprising:
a clock generation unit to generate first and second phases of a clock signal;
a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampling unit to generate a sampled differential signal;
a differential amplifier to amplify the sampled differential signal; and
a first switch for coupling a first output of the differential amplifier with an input of the differential amplifier, wherein the first switch is operable by the second phase of the clock signal.

17. The apparatus of claim 16 further comprises a second switch for coupling a second output of the differential amplifier with another input of the differential amplifier, wherein the second switch is operable by the second phase of the clock signal.

18. A method comprising:
generating first and second phases of a clock signal;
sampling a differential input signal according to the first and second phases of the clock signal, the sampling to generate a sampled differential signal using a sampling unit comprising a first switch to sample a first signal of the differential input signal to generate a first sampled signal of the sampled differential signal, and a second switch to sample a second signal of the differential input signal to generate a second sampled signal of the sampled differential signal, wherein the first and second switches are operable by the first phase of the clock signal; and
amplifying the sampled differential signal to generate an output signal.

19. The method of claim 18 further comprising:
turning on or off a logic unit according to the output signal.

20. A system comprising:
a wireless connectivity;
a processor, communicatively coupled to the wireless connectivity, the processor having an input-output (I/O) receiver including:
a clock generation unit to generate first and second phases of a clock signal;
a sampling unit to sample a differential input signal according to the first and second phases of the clock signal, the sampler to generate a sampled differential signal, wherein the sampling unit comprises
a first switch to sample a first signal of the differential input signal to generate a first sampled signal of the sampled differential signal, and
a second switch to sample a second signal of the differential input signal to generate a second sampled signal of the sampled differential signal, wherein the first and second switches are operable by the first phase of the clock signal; and

a differential amplifier to amplify the sampled differential signal; and

a display unit.

21. The system of claim 20 further comprises:
a logic unit to receive an output of the differential amplifier, wherein the logic unit is operable to be turned on or off according to the output of the differential amplifier.

22. The system of claim 20 , wherein the display unit is a touch screen.

Assignees

• Song Hongjiang
• Le Dianbo
• Intel Corp

Inventors

• Song Hongjiang
• Le Dianbo

Classifications

• H04L7/10

  Arrangements for initial synchronisation · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H04L7/0079 Primary

  Receiver details · CPC title

• H03F2203/45551

  the IC comprising one or more switched capacitors · CPC title

• H03F2203/45514

  the FBC comprising one or more switched capacitors, and being coupled between the LC and the IC · CPC title