RF power detector and detection method

Patent metadata

Field	Value
Publication number	US-9362898-B2
Application number	US-201414478780-A
Country	US
Kind code	B2
Filing date	Sep 5, 2014
Priority date	Sep 30, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

The invention provides an RF detection circuit and method using an envelope detector having an output connected to a first input of a differential amplifier and a reference storage capacitor to a second input of the differential amplifier. In a preferred implementation of the calibration mode, there is initial discharging of a reference storage capacitor, high speed charging of the reference storage capacitor until the differential amplifier output toggles, then slower discharging of the reference storage capacitor until the differential amplifier output toggles again. The resulting voltage is stored on the reference storage capacitor for use in a subsequent detection mode. This provides storage of an offset voltage which calibrates both the envelope detector differential amplifier functions.

First claim

The invention claimed is:

1. An RF detector circuit, comprising:
an envelope detector having an output capacitor on which an envelope detection signal is provided;
a reference storage capacitor for storing a reference voltage;
a differential amplifier having a first input coupled to the output capacitor and a second input coupled to the reference storage capacitor;
a reset circuit;
a charging circuit for charging the reference storage capacitor at a first rate; and
a discharge circuit for discharging the reference storage capacitor at a second, different, rate; and a controller, for controlling the sequence of charging and discharging the reference storage capacitor to store an amplifier offset voltage on the reference storage capacitor based on toggling of the amplifier output during the charging or discharging operation which has the slower rate.

2. A circuit as claimed in claim 1 , wherein the envelope detector circuit comprises a transistor with the input signal applied to the transistor gate, and connected to a power rail through a load resistor, and an output smoothing capacitor connected to a node between the transistor and the load resistor.

3. A circuit as claimed in claim 1 , wherein the reset circuit comprises an initial discharge circuit for discharging the reference storage capacitor, and wherein the first rate is greater than the second rate.

4. A circuit as claimed in claim 3 , wherein the initial discharge circuit comprises a switch between the reference storage capacitor and ground.

5. A circuit as claimed in claim 1 , wherein the discharge circuit comprises a current source driving a current to ground, and an isolation switch enabling the current source to be selectively coupled to the reference storage capacitor.

6. A circuit as claimed in claim 5 , wherein the charging circuit comprises a current source, driving a current to the reference storage capacitor, when enabled by a switch.

7. A circuit as claimed in claim 6 , wherein current source of the faster of the charging circuit and discharging circuit has a current delivery of at least 50 times the current delivery of the slower of the charging circuit and the discharge circuit.

8. A circuit as claimed in claim 1 , comprising an input switch for connecting the circuit input to ground for a calibration mode, or to an RF input for a receive mode.

9. A circuit as claimed in claim 1 , wherein the controller is for controlling the timing of operation of switches which control the or each discharge circuit and the charging circuit.

10. A circuit as claimed in claim 1 , wherein the envelope detector output is connected to the inverting input of the differential amplifier and the reference storage capacitor is connected to the non-inverting input of the differential amplifier.

11. A circuit as claimed in claim 1 , wherein the circuit input is connected to the non-inverting input of the differential amplifier through a resistor.

12. An RF detection method, using an RF detector circuit which comprises an envelope detector having an output connected to a first input of a differential amplifier and a reference storage capacitor to a second input of the differential amplifier, the method comprising:
in a calibration mode:
coupling an input of the RF detector circuit to a reference potential;
performing a reset operation of the voltage on the reference storage capacitor;
charging the reference storage capacitor at a first rate until the differential amplifier output toggles and discharging the reference storage capacitor at a second lower rate until the differential amplifier output toggles, or discharging the reference storage capacitor at the first rate until the differential amplifier output toggles and charging the reference storage capacitor at a second lower rate until the differential amplifier output toggles; and
storing the resulting voltage on the reference storage capacitor; and in a detection mode:
coupling the input of the RF detector circuit to a signal to be detected.

13. A method as claimed in claim 12 , wherein performing the reset operation comprises fully discharging the reference storage capacitor, and wherein the charging is carried out before the discharging and with a higher rate.

14. A method as claimed in claim 12 , wherein charging the reference storage capacitor comprises driving a first current from a current source to the reference storage capacitor.

15. A method as claimed in claim 14 , wherein discharging the reference storage capacitor comprises driving a second current from the reference storage capacitor to a second current source, wherein one current source delivers at least 50 times the current of the other current source.

Assignees

• Nxp Bv

Inventors

• Chandernagor Lucie
• Jean Patrick

Classifications

• H03F3/45995

  using switching means · CPC title

• H04B10/6933

  Offset control of the differential preamplifier · CPC title

• H03K5/003 Primary

  Changing the DC level (reinsertion of DC component of a television signal H04N5/16) · CPC title

• H03F3/19

  with semiconductor devices only · CPC title