Semiconductor integrated circuit and operating method thereof

Patent metadata

Field	Value
Publication number	US-9362742-B2
Application number	US-201313899596-A
Country	US
Kind code	B2
Filing date	May 22, 2013
Priority date	May 28, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Disclosed are a semiconductor integrated circuit including first and second supply terminals; an input voltage selection circuit including a power-on reset circuit, an input voltage detection circuit, a control circuit and a power-on reset auxiliary circuit; and first and second power supply switches, and its operating method. When the above detection circuit detects the supply of both first and second power supply voltages to both supply terminals upon completion of a power on reset operation of the reset circuit, the control circuit controls either of both power supply switches, having a high priority of preset priorities, to an on state. After its control, the auxiliary circuit detects a power failure in the power supply voltage supplied to the high-priority power supply switch. The reset circuit performs another power on reset operation. The control circuit controls the power supply switch having a low priority of the priorities to an on state.

First claim

What is claimed is:

1. A semiconductor integrated circuit comprising:
a first supply terminal capable of supplying a first power supply voltage;
a second supply terminal capable of supplying a second power supply voltage;
an input voltage selection circuit coupled to the first supply terminal and the second supply terminal;
a first power supply switch; and
a second power supply switch,
wherein the input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit, a control circuit and a power-on reset auxiliary circuit,
wherein when the input voltage detection circuit detects the supply of either of the first and second power supply voltages to either of the first and second supply terminals at the end of a power on reset operation of the power-on reset circuit, the control circuit responsive to the detection thereof controls either of the first and second power supply switches, corresponding to the supply terminal at which said supply has been detected, to an on state,
wherein when the input voltage detection circuit detects the supply of both of the first and second power supply voltages to both of the first and second supply terminals at the end of a power on reset operation of the power-on reset circuit, the control circuit responsive to the detection thereof controls either of the first and second power supply switches, having a high priority of priorities set in advance, to an on state,
wherein after the power supply switch having the high priority has been controlled to the on state, the power-on reset auxiliary circuit detects a power failure in the power supply voltage supplied to the power supply switch having the high priority, of the first and second power supply voltages,
wherein the power-on reset circuit performs another power on reset operation in response to a result of detection of the power failure by the power-on reset auxiliary circuit, and
wherein at the end of said another power on reset operation of the power-on reset circuit, the control circuit controls either of the first and second power supply switches, having a low priority of the priorities set in advance, to an on state,
wherein the power-on reset circuit generates a power on reset signal in response to the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal,
wherein the input voltage detection circuit generates a first voltage detection output signal in response to the supply of the first power supply voltage to the first supply terminal, and the input voltage detection circuit generates a second voltage detection output signal in response to the supply of the second power supply voltage to the second supply terminal,
wherein the control circuit controls the first power supply switch and the second power supply switch in response to the power on reset signal, the first voltage detection output signal and the second voltage detection output signal,
wherein at a timing of a change in the level of the power on reset signal responsive to the end of a power on reset operation of the power-on reset circuit, the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal,
wherein in a first case where at the timing of the change in the level of the power on reset signal, the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal but does not detect the supply of the second power supply voltage to the second supply terminal, the control circuit controls the first power supply switch and the second power supply switch to an on state and an off state respectively after the end of the power on reset operation,
wherein the first power supply switch controlled to the on state supplies the first power supply voltage supplied to the first supply terminal to a load by the control of the first power supply switch and the second power supply switch to the on state and the off state respectively after the end of the power on reset operation,
wherein in a second case where at the timing of the change in the level of the power on reset signal, the input voltage detection circuit detects the supply of the second power supply voltage to the second supply terminal but does not detect the supply of the first power supply voltage to the first supply terminal, the control circuit controls the first power supply switch and the second power supply switch to an off state and an on state respectively after the end of the power on reset operation,
wherein the second power supply switch controlled to the on state supplies the second power supply voltage supplied to the second supply terminal to the load by the control of the first power supply switch and the second power supply switch to the off state and the on state respectively after the end of the power on reset operation,
wherein in a third case where at the timing of the change in the level of the power on reset signal, the input voltage detection circuit detects the supply of the first power supply voltage to the first supply terminal and the supply of the second power supply voltage to the second supply terminal, the control circuit controls one of the first power supply switch and the second power supply switch and the other thereof to an on state and an off state respectively after the end of the power on reset operation,
wherein in the third case, the one of the first power supply switch and the second power supply switch and the other thereof are respectively controlled to the on state and the off state in accordance with the order of precedence set to the control circuit in advance, and
wherein the one thereof controlled to the on state, corresponding to the power supply switch having the high priority supplies the first power supply voltage supplied to the first supply terminal or the second power supply voltage supplied to the second supply terminal to the load.

2. The semiconductor integrated circuit according to claim 1 , wherein the power-on reset auxiliary circuit includes first and second reference voltage generators, first and second differential amplifiers and first and second N channel MOS transistors,
wherein the second power supply voltage supplied to the second supply terminal is supplied to the first reference voltage generator and the first differential amplifier as an operating power supply voltage, a first reference voltage generated from the first reference voltage generator is supplied to a non-inversion input terminal of the first differential amplifier, and an inversion input terminal of the first differential amplifier is responsive to the first power supply voltage supplied to the first supply terminal,
wherein a gate of the first N channel MOS transistor is driven by an output signal of the first differential amplifier, and a source and drain of the first N channel MOS transistor are coupled to a ground potential and the power-on reset circuit respectively,
wherein the first power supply voltage supplied to the first supply terminal is supplied to the second reference voltage generator and the second differential amplifier as an operating power supply voltage, a second reference voltage generated from the second reference voltage generator is supplied to a non-inversion input terminal of the second differential amplifier, and an inversion input terminal of the second differential amplifier is responsive to the second power supply voltage supplied to the second supply terminal,
wherein a gate of the second N channel MOS transistor is driven by an output signal of the second differential amplifier, and a source and drain of the second N channel MOS transistor are coupled to the ground potential and the power

Assignees

• Renesas Electronics Corp

Inventors

• Kayama Masanori

Classifications

• H02J2207/40

  adapted for charging from various sources, e.g. AC, DC or multivoltage · CPC title

• G06F1/28

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• H02J9/06 Primary

  with automatic change-over {, e.g. UPS systems} · CPC title

• H02J1/00 Primary

  Circuit arrangements for DC mains or DC distribution networks · CPC title

• H02J7/0055

  Electricity · mapped topic