Power device termination structures and methods

Patent metadata

Field	Value
Publication number	US-9362394-B2
Application number	US-201414307678-A
Country	US
Kind code	B2
Filing date	Jun 18, 2014
Priority date	Jun 18, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Power device termination structures and methods are disclosed herein. The structures include a trenched-gate semiconductor device. The trenched-gate semiconductor device includes a semiconducting material and an array of trenched-gate power transistors. The array defines an inner region including a plurality of inner transistors and an outer region including a plurality of outer transistors. The inner transistors include a plurality of inner trenches that has an average inner region spacing. The outer transistors include a plurality of outer trenches that has an average termination region spacing. The average termination region spacing is greater than the average inner region spacing or is selected such that a breakdown voltage of the plurality of outer transistors is greater than a breakdown voltage of the plurality of inner transistors.

First claim

What is claimed is:

1. A trenched-gate semiconductor device, comprising:
a semiconducting material; and
an array of trenched-gate power transistors that defines an inner region including a plurality of inner transistors and a termination region including a plurality of outer transistors, wherein:
the plurality of inner transistors comprises a plurality of inner trenches that has an average inner region spacing as defined between each of the plurality of inner trenches and a closest other of the plurality of inner trenches;
the plurality of outer transistors comprises a plurality of outer trenches that has an average termination region spacing as defined between each of the plurality of outer trenches and a closest one of the plurality of inner trenches;
the average termination region spacing is at least 105% and less than 120% of the average inner region spacing; and
each transistor in the array of trenched-gate power transistors comprises an electrically conductive gate that extends within a trench, which is defined within the semiconducting material, and a gate oxide, which electrically separates the electrically conductive gate from the semiconducting material.

2. The device of claim 1 , wherein the semiconducting material defines a plurality of columns that extends between adjacent trenches in the array of trenched-gate power transistors.

3. The device of claim 2 , wherein each column of the plurality of columns comprises a source region of a first conductivity type, a drain drift region of the first conductivity type, and a body region of a second conductivity type, wherein the body region extends between the source region and the drain drift region and in contact with the gate oxide to define a channel region.

4. The device of claim 3 , wherein each column further comprises a RESURF region that is configured to form a depletion region within the drain drift region.

5. The device of claim 1 , wherein the plurality of inner transistors comprises:
a plurality of intermediate transistors, wherein:
each intermediate transistor extends between a respective one of the plurality of outer transistors and a respective other of the plurality of inner transistors;
the plurality of intermediate transistors comprises a plurality of intermediate trenches having an average intermediate region spacing defined between each of the plurality of intermediate trenches and a nearest other of the plurality of inner trenches;
the average termination region spacing is defined between the plurality of intermediate trenches and the plurality of outer trenches and is greater than 110% and less than 120% of the average inner region spacing; and
the average intermediate region spacing is at least 105% and less than 110% of the average inner region spacing.

6. The device of claim 1 , wherein at least one of:
(i) an average inner trench width of the plurality of inner trenches is nominally equal to an average outer trench width of the plurality of outer trenches;
(ii) an average inner trench depth of the plurality of inner trenches is nominally equal to an average outer trench depth of the plurality of outer trenches; and
(iii) a spacing between each of the plurality of inner trenches and the closest other of the plurality of inner trenches is nominally constant.

7. The device of claim 1 , wherein the array of trenched-gate power transistors is a two-dimensional array of trenched-gate power transistors in which the plurality of inner transistors is surrounded by the plurality of outer transistors.

8. The device of claim 1 , wherein each of the plurality of inner trenches further comprises:
an electrically conductive field plate that is located below a respective electrically conductive gate within a respective inner trench of the plurality of inner trenches, wherein:
the electrically conductive field plate is electrically connected to a ground plane of the device, and
the electrically conductive field plate is electrically separated from the semiconducting material by a thick isolating oxide and from the respective electrically conductive gate by a thin isolating oxide.

9. A method of forming a trenched-gate semiconductor device, the method comprising:
forming a plurality of inner trenches within a semiconducting material to define an inner region of an array of trenched-gate power transistors, wherein the plurality of inner trenches has an average inner region spacing as defined between each of the plurality of inner trenches and a closest other of the plurality of inner trenches; and
forming a plurality of outer trenches within the semiconducting material to define a termination region of the array of trenched-gate power transistors, wherein the plurality of outer trenches has an average termination region spacing as defined between each of the plurality of outer trenches and a closest one of the plurality of inner trenches, and further wherein the average termination region spacing is at least 105% and less than 120% of the average inner region spacing.

10. The method of claim 9 , wherein the method further comprises:
forming a gate oxide within each of the plurality of inner trenches and within each of the plurality of outer trenches; and
forming an electrically conductive gate within each of the plurality of inner trenches and within each of the plurality of outer trenches, wherein the gate oxide electrically separates the electrically conductive gate from the semiconducting material.

11. The method of claim 10 , wherein the forming the plurality of inner trenches and the forming the plurality of outer trenches comprises forming a plurality of columns of the semiconducting material, wherein the plurality of columns extends between adjacent trenches in the array of trenched-gate power transistors.

12. The method of claim 11 , wherein each column of the plurality of columns comprises a respective source region of a first conductivity type and a respective drain drift region of the first conductivity type, and wherein the method further comprises:
forming a respective body region of a second conductivity type in each column of the plurality of columns, wherein the respective body region extends between the respective source region and the respective drain drift region and in contact with the gate oxide to define a channel region.

13. The method of claim 10 , wherein, subsequent to the forming the gate oxide and prior to the forming the electrically conductive gate, the method further comprises forming an electrically conductive field plate within each of the plurality of inner trenches and subsequently forming a thin isolating oxide on the electrically conductive field plate such that the thin isolating oxide extends between the electrically conductive field plate and the electrically conductive gate.

14. The method of claim 9 , wherein the plurality of inner trenches comprises a plurality of intermediate trenches, wherein each of the plurality of intermediate trenches extends between a respective one of the plurality of outer trenches and a respective one of a remainder of the plurality of inner trenches, wherein the plurality of intermediate trenches has an average intermediate region spacing as defined between each of the plurality of intermediate trenches and the respective one of the remainder of the plurality of inner trenches, wherein the average termination region spacing is defined between the plurality of intermediate trenches and the plurality of outer trenches, and further wherein the method comprises:
forming the plurality of inner trenches, the plurality of intermediate trenches, and the plurality of outer trenches such that

Assignees

• Zitouni Moaniss
• De Frésart Edouard D
• Ku Pon Sung
• Qin Ganming
• Freescale Semiconductor Inc

Inventors

• Zitouni Moaniss
• De Frésart Edouard D
• Ku Pon Sung
• Qin Ganming

Classifications

• H10P76/00

  Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography · CPC title

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/20

  Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title