Double diffused metal oxide semiconductor device and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9362384-B2
Application number	US-201414559542-A
Country	US
Kind code	B2
Filing date	Dec 3, 2014
Priority date	Dec 25, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

First claim

What is claimed is:

1. A manufacturing method of a double diffused metal oxide semiconductor (DMOS) device, comprising:
providing a first conductive type substrate, which has an upper surface;
forming a second conductive type high voltage well in the substrate below the upper surface;
forming a gate on the upper surface, wherein at least part of the gate is located in the high voltage well from top view, and the gate has a first side and a second side opposite to each other in a vertical direction;
forming a first conductive type body region in the high voltage well below the upper surface, wherein at least part of the body region is located outside the first side;
forming a source and a drain with the second conductive type below the upper surface outside the gate, the source being located in the body region outside the first side, and the drain being located outside the second side, wherein the drain and the gate are separated by the high voltage well, and when the DMOS device turns ON, a lateral channel is formed between the source and the drain below the upper surface;
forming a first conductive type body electrode in the body region below the upper surface as an electrically contact of the body region; and
forming a first conductive type floating region in the body region below the upper surface, wherein the floating region is electrically floating and electrically isolated from the source and the gate,
wherein the floating region separates the source to a first source and a second source in the vertical direction, and the floating region and the source are separated by part of the body region.

2. The manufacturing method of claim 1 , wherein the DMOS device is a double diffused drain metal oxide semiconductor (DDDMOS) device or a lateral double diffused metal oxide semiconductor (LDMOS) device.

3. The manufacturing method of claim 1 , wherein the floating region and the body electrode are formed by a same process step.

Assignees

• Kao Tzu-Cheng
• Lee Jian-Hsing
• Su Jin-Lian
• Chu Huan-Ping
• Su Hung-Der
• Richtek Technology Corp

Inventors

• Kao Tzu-Cheng
• Lee Jian-Hsing
• Su Jin-Lian
• Chu Huan-Ping
• Su Hung-Der

Classifications

• H10D62/127

  of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs · CPC title

• H10D62/393

  Body regions of DMOS transistors or IGBTs  (cell layout of DMOS H10D62/127) · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D30/0285 Primary

  using formation of insulating sidewall spacers · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title