Transfer-free batch fabrication of single layer graphene devices

Patent metadata

Field	Value
Publication number	US-9362364-B2
Application number	US-201013384663-A
Country	US
Kind code	B2
Filing date	Jul 21, 2010
Priority date	Jul 21, 2009
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A method of manufacturing one or more graphene devices is disclosed. A thin film growth substrate is formed directly on a device substrate. Graphene is formed on the thin film growth substrate. A transistor is also disclosed, having a device substrate and a source supported by the device substrate. The transistor also has a drain separated from the source and supported by the device substrate. The transistor further has a single layer graphene (SLG) channel grown partially on and coupling the source and the drain. The transistor also has a gate aligned with the SLG channel, and a gate insulator between the gate and the SLG channel. Integrated circuits and other apparati having a device substrate, a thin film growth substrate formed directly on at least a portion of the device substrate, and graphene formed directly on at least a portion of the thin film growth substrate are also disclosed.

First claim

What is claimed is:

1. A method of manufacturing one or more graphene devices, comprising:
forming a thin film growth substrate directly on a device substrate;
forming a graphene layer on the thin film growth substrate;
processing the graphene layer and the thin film growth substrate to form a patterned graphene layer upon a patterned thin film growth substrate; and
undercutting the patterned thin film growth substrate with respect to the patterned graphene layer formed upon the patterned thin film growth substrate to provide an undercut patterned thin film growth substrate having the patterned graphene layer formed upon the undercut patterned thin film growth substrate.

2. The method of claim 1 , wherein the device substrate comprises silicon.

3. The method of claim 2 , wherein the device substrate further comprises silicon dioxide.

4. The method of claim 1 , wherein the device substrate comprises a semiconductor.

5. The method of claim 1 , wherein the device substrate comprises a material selected from the group consisting of glass, fused silica, quartz, sapphire, and a metal.

6. The method of claim 1 , wherein the thin film growth substrate comprises copper.

7. The method of claim 6 , wherein the thin film growth substrate further comprises a nickel adhesion layer.

8. The method of claim 1 , wherein the thin film growth substrate comprises an element selected from the group consisting of nickel, cobalt, ruthenium, iridium; and a transition metal.

9. The method of claim 1 , wherein the thin film growth substrate comprises a plurality of thin film growth substrate areas which are not continuous with each other.

10. The method of claim 1 , wherein the thin film growth substrate has a prepatterned structure.

11. The method of claim 1 , wherein forming the thin film growth substrate directly on the device substrate comprises evaporating the thin film growth substrate directly on the device substrate.

12. The method of claim 1 , wherein forming the thin film growth substrate directly on the device substrate comprises sputtering the thin film growth substrate directly on the device substrate.

13. The method of claim 1 , wherein forming the thin film growth substrate directly on the device substrate comprises electroplating the thin film growth substrate directly on the device substrate.

14. The method of claim 1 , wherein the thin film growth substrate has a thickness of at least approximately 100 nanometers.

15. The method of claim 1 , further comprising removing at least a first portion of a metallic oxide from the thin film growth substrate before forming graphene on the thin film growth substrate.

16. The method of claim 15 , wherein removing at least the first portion of the metallic oxide from the thin film growth substrate comprises immersing the thin film growth substrate in an acidic reagent configured to react with and remove oxygen atoms of the metallic oxide.

17. The method of claim 16 , wherein the acidic reagent comprises an acetic acid.

18. The method of claim 17 , wherein immersing the thin film growth substrate in the acidic reagent comprises immersing the thin film growth substrate in the acetic acid for approximately ten minutes at a temperature of approximately 35 degrees Celsius.

19. The method of claim 1 , wherein forming graphene on the thin film growth substrate comprises forming graphene on the thin film growth substrate in a chemical vapor deposition (CVD) process.

20. The method of claim 19 , wherein the CVD process comprises: heating the thin film growth substrate for approximately 20 minutes at approximately 1000 degrees Celsius in a growth environment of approximately 200 standard cubic centimeters per minute (sccm) hydrogen (H.sub.2) and approximately 875 sccm methane (CH.sub.4) at a pressure of approximately 11 Torr.

21. The method of claim 19 , wherein forming graphene on the thin film growth substrate comprises forming a substantially single layer of graphene on the thin film growth substrate.

22. A method of manufacturing one or more graphene devices, comprising:
forming a thin film growth substrate directly on a device substrate;
forming a graphene layer on the thin film growth substrate;
processing the graphene layer and the thin film growth substrate to form a patterned graphene layer upon a patterned thin film growth substrate;
coating at least a portion of the graphene with a photoresist layer;
patterning the photoresist layer to define the one or more graphene devices under a remaining photoresist pattern;
removing graphene not protected by the remaining photoresist pattern;
removing the thin film growth substrate not protected by the remaining photoresist pattern; and
removing at least part of the remaining photoresist pattern.

23. The method of claim 22 , wherein at least one of the defined one or more graphene devices comprises a pair of pads connected by a graphene channel.

24. The method of claim 23 , wherein, after removing graphene and thin film growth substrate not protected by the remaining photoresist pattern: each pad in the pair of pads for the at least one of the one or more graphene devices comprises a remaining area of the thin film growth substrate.

25. The method of claim 22 , wherein patterning the photoresist layer to define one or more graphene devices under the remaining photoresist pattern comprises removing unwanted photoresist residue from the photoresist layer.

26. The method of claim 25 , wherein removing unwanted photoresist residue from the photoresist layer comprises plasma etching the unwanted photoresist residue.

27. The method of claim 26 , wherein plasma etching the unwanted photoresist residue also removes said graphene not protected by the remaining photoresist pattern.

28. The method of claim 22 , wherein removing said thin film growth substrate not protected by the remaining photoresist pattern comprises exposing the thin film growth substrate to an etch solution.

29. The method of claim 22 , wherein said removing at least part of the remaining photoresist pattern occurs after the thin film growth substrate is removed.

30. The method of claim 1 , further comprising treating the patterned graphene layer formed upon the undercut patterned thin film growth substrate to provide a treated patterned graphene layer that passivates sidewalls of the undercut patterned thin film growth substrate.

31. An apparatus, comprising
a device substrate;
a patterned thin film growth substrate formed directly on at least a portion of the device substrate and comprising at least two patterned thin film growth substrate pads which include sidewalls; and
a patterned graphene layer formed directly on at least a portion of the patterned thin film growth substrate, including the at least two patterned thin film growth substrate pads, the patterned thin film growth substrate being undercut in comparison with the patterned graphene layer which extends beyond the sidewalls of the at least two patterned thin film growth substrate pads and bridges between the at least two patterned thin film growth substrate pads and which also passivates the sidewalls of the at least two patterned thin film growth substrate pads.

32. The apparatus of claim 31 , wherein the device substrate comprises silicon.

33. The appa

Assignees

• Park Jiwoong
• Ruiz-Vargas Carlos
• Levendorf Mark Philip
• Brown Lola
• Univ Cornell

Inventors

• Park Jiwoong
• Ruiz-Vargas Carlos
• Levendorf Mark Philip
• Brown Lola

Classifications

• H10D87/00

  Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate · CPC title

• H10D84/08

  using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies · CPC title

• H10D30/6758

  characterised by the insulating substrates · CPC title

• H10D30/6741

  Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755) · CPC title

• H10D30/6734

  having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs · CPC title