Threshold voltage control for mixed-type non-planar semiconductor devices

Patent metadata

Field	Value
Publication number	US-9362284-B2
Application number	US-201514924486-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Jun 26, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

First claim

The invention claimed is:

1. A gate structure for a non-planar semiconductor device, the gate structure comprising:
a high-k dielectric layer lining inner surfaces of a gate opening of a non-planar semiconductor device;
a first layer of p-type work function metal over the high-k dielectric layer;
an etch stop layer over the first layer of p-type work function metal;
a layer of n-type work function metal over the etch stop layer; and
a layer of conductive material over the layer of n-type work function metal, the conductive layer filling a remaining open space of the gate opening.

2. The gate structure of claim 1 , wherein the gate opening comprises a gate opening of a p-type non-planar semiconductor device, the gate structure further comprising a diffusion barrier layer and at least one second layer of p-type work function metal between the diffusion barrier layer and the second layer of p-type work function metal.

3. The gate structure of claim 2 , wherein the second layer of p-type work function metal has been oxidized.

4. The gate structure of claim 1 , further comprising a gate opening of a n-type non-planar semiconductor device, the gate structure also being present in the n-type device gate opening.

5. The gate structure of claim 1 , wherein the gate opening comprises a gate opening of a n-type non-planar semiconductor device, wherein the barrier layer comprises a first barrier layer and a second barrier layer, the gate structure further comprising a second layer of p-type work function metal between the first and second barrier layers.

6. The gate structure of claim 1 , wherein the gate opening comprises a gate opening of a n-type non-planar semiconductor device, and wherein a lower portion of the barrier layer has been implanted with a material that lowers n-type threshold voltage.

7. The gate structure of claim 6 , wherein the n-type threshold voltage lowering material comprises one of arsenic, argon, silicon and germanium.

Assignees

• Globalfoundries Inc

Inventors

• Togo Mitsuhiro
• Xiao Changyong
• Liu Yiqun
• Triyoso Dina H
• Pal Rohit

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D86/011

  comprising FinFETs · CPC title