FinFET with multilayer fins for multi-value logic (MVL) applications and method of forming

Patent metadata

Field	Value
Publication number	US-9362277-B2
Application number	US-201414175827-A
Country	US
Kind code	B2
Filing date	Feb 7, 2014
Priority date	Feb 7, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

First claim

What is claimed is:

1. A method comprising:
forming plural fins on a silicon substrate, each fin covered with a hardmask;
filling spaces between the fins and hard masks with an oxide;
removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin;
forming plural silicon-based (Si-based) layers in each cavity with an increasing percentage of germanium (Ge) or carbon (C) content or with an increasing concentration of dopant from a bottom layer to a top layer;
performing CMP for planarization to a top of the fins;
recessing the oxide to a depth slightly below a top portion of the fins having a thickness equal to a thickness of each Si-based layer; and
forming a high-k gate dielectric and metal gate electrode over the plural Si-based layers.

2. The method according to claim 1 , comprising removing the hardmask from the fins with hot phosphorus and recessing the fins by plasma Si etching.

3. The method according to claim 2 , comprising forming each cavity to a depth of 40 nanometers (nm), wherein each cavity has an aspect ratio of 5:1 or less.

4. The method according to claim 1 , comprising forming each layer to a thickness of 10 to 15 nm.

5. The method according to claim 1 , comprising forming the layers sequentially by epitaxial growth.

6. The method according to claim 5 , comprising forming the layers by selective epi growth (SEG) of silicon germanium (SiGe) with an increasing percentage of Ge.

7. The method according to claim 6 , wherein the percentage of Ge ranges from 0 to 50%.

8. The method according to claim 5 , forming the layers by SEG of carbon-doping silicon (Si:C) with an increasing percentage of C.

9. The method according to claim 8 , wherein the percentage of C ranges from 0 to 2%.

10. The method according to claim 5 , comprising forming the layers by SEG with in situ doped silicon (Si) with a decreasing concentration of dopant.

11. The method according to claim 10 , wherein the concentration of dopant ranges from 1E18 to 1E20.

12. A method comprising:
forming plural fins on a silicon substrate, each fin covered with a hardmask;
filling spaces between the fins and hardmasks with an oxide;
planarizing the oxide;
removing the hardmasks and recessing each fin with hot phosphorus, forming a cavity to a depth of 40 nanometers (nm) in the oxide over each fin;
masking cavities over fins for p-FinFETs, exposing fins for n-FinFETS;
epitaxially growing plural silicon-based (Si-based) layers in each cavity with a percentage of carbon (C) increasing between 0 and 2% or with a concentration of p-type dopant decreasing between 1E18 and 1E20 from a bottom layer to a top layer;
masking cavities over fins for n-FinFETs, exposing fins for p-FinFETS;
epitaxially growing plural Si-based layers in each cavity with a percentage of germanium (Ge) increasing between 0 and 50% or with a concentration of n-type dopant decreasing between 1E18 and 1E20 from a bottom layer to a top layer;
recessing the oxide to a top of the fins to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and
forming a high-k gate dielectric and metal gate electrode over the plural Si-based layers and wrapped around the fins.

Assignees

• Globalfoundries Inc
• Globalfounries Inc

Inventors

• Chi Min-Hwa
• Jacob Ajey
• Paul Abhijeet

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P14/3444

  P-type · CPC title

• H10P14/3442

  N-type · CPC title

• H10P14/3408

  Silicon carbide · CPC title

• H10P52/402

  of semiconductor materials · CPC title