Semiconductor integrated circuit device with transistor and non-transistor regions

Patent metadata

Field	Value
Publication number	US-9362268-B2
Application number	US-201213547651-A
Country	US
Kind code	B2
Filing date	Jul 12, 2012
Priority date	Jul 25, 2011
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

In a high-frequency circuit, it is necessary to provide galvanic blocking between active elements such as transistors and between an active element and an external terminal, and thus MIM capacitors or the like are used frequently. A MIM capacitor coupled to an external terminal is easily affected by static electricity from outside and causes a problem of electro-static breakdown or the like. In a MIM capacitor formed over a semi-insulating compound semiconductor substrate, a first electrode thereof is coupled to an external pad and to the semi-insulating compound semiconductor substrate, and a second electrode thereof is coupled to the semi-insulating compound semiconductor substrate.

First claim

What is claimed is:

1. A semiconductor integrated circuit device, comprising:
(a) a semi-insulating compound semiconductor substrate having a first major surface;
(b) a transistor region and a non-transistor region disposed over the first major surface of the semi-insulating compound semiconductor substrate;
(c) a first conductive epitaxial compound semiconductor film disposed over and on the first major surface of the semi-insulating compound semiconductor substrate only within the transistor region;
(d) a first insulating film disposed over the semi-insulating compound semiconductor substrate within the non-transistor region;
(e) an external electrode pad disposed in an upper layer of the first insulating film within the non-transistor region;
(f) a first metal substrate contact portion electrically coupled to the external electrode pad within the non-transistor region;
(g) a Metal-Insulator-Metal (MIM) capacitor disposed within the non-transistor region and having a first capacitor electrode and a second capacitor electrode disposed within the non-transistor region; and
(h) a semi-insulating surface layer, having a different material composition than the first conductive epitaxial compound semiconductor film, disposed only within the non-transistor region over and on the first major surface of the semi-insulating compound semiconductor substrate in a layer lower than the first insulating film, and having a resistivity lower than the semi-insulating compound semiconductor substrate,
wherein the first capacitor electrode is electrically coupled to the external electrode pad and the first metal substrate contact portion within the non-transistor region,
the first insulating film is disposed between the second capacitor electrode and the semi-insulating surface layer,
the second capacitor electrode is electrically coupled to a second metal substrate contact portion within the non-transistor region,
the first metal substrate contact portion and the second metal substrate contact portion are disposed in a layer below the second capacitor electrode within the non-transistor region, and
the first metal substrate contact portion and the second metal substrate contact portion are both disposed directly on the semi-insulating surface layer and electrically coupled to the semi-insulating compound semiconductor substrate via the semi-insulating surface layer.

2. The semiconductor integrated circuit device according to claim 1 ,
wherein the first metal substrate contact portion is provided directly under the external electrode pad.

3. The semiconductor integrated circuit device according to claim 1 ,
wherein the second capacitor electrode is a lower electrode of the MIM capacitor.

4. The semiconductor integrated circuit device according to claim 1 ,
wherein the second capacitor electrode is electrically coupled to a source or drain terminal of a high electron mobility transistor (HEMT).

5. The semiconductor integrated circuit device according to claim 1 ,
wherein each of the semi-insulating compound semiconductor substrate and the semi-insulating surface layer mainly includes a GaAs-based member.

6. The semiconductor integrated circuit device according to claim 1 , further comprising:
a high electron mobility transistor (HEMT) disposed within the transistor region and electrically coupled to the MIM capacitor.

7. The semiconductor integrated circuit device according to claim 1 , wherein the first metal substrate contact portion and the second metal substrate contact portion are disposed in a same layer as the first insulating film.

8. The semiconductor integrated circuit device according to claim 1 , wherein the MIM capacitor is disposed over the first insulating film.

9. The semiconductor integrated circuit device according to claim 1 , wherein the first capacitor electrode is electrically coupled to the external electrode pad, the first metal substrate contact portion and the semi-insulating compound semiconductor substrate within the non-transistor region.

10. The semiconductor integrated circuit device according to claim 1 , wherein the semi-insulating surface layer is only within the non-transistor region over the first major surface of the semi-insulating compound semiconductor substrate in a layer lower than the first insulating film and is laterally in contact with the first conductive epitaxial compound semiconductor film.

11. The semiconductor integrated circuit device according to claim 1 , wherein the composition of the semi-insulating surface layer includes implanted fluorine, helium, boron, or hydrogen ions.

Assignees

• Kurokawa Atsushi
• Osakabe Shinya
• Renesas Electronics Corp

Inventors

• Kurokawa Atsushi
• Osakabe Shinya

Classifications

• H10W20/496

  Capacitor integral with wiring layers · CPC title

• H10D84/641

  Combinations of only vertical BJTs (vertical complementary BJTs H10D84/673) · CPC title

• H10D84/82

  of only field-effect components · CPC title

• H10D84/05

  using Group III-V technology · CPC title

• H10D84/01

  Manufacture or treatment · CPC title