Radio frequency shielding within a semiconductor package

Patent metadata

Field	Value
Publication number	US-9362233-B2
Application number	US-201313931902-A
Country	US
Kind code	B2
Filing date	Jun 29, 2013
Priority date	Jun 29, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and an isolation layer between the digital chip and the radio frequency chip. A cover encloses the digital chip and the radio frequency chip.

First claim

What is claimed is:

1. A multiple chip package comprising:
a digital chip;
a first redistribution layer adjacent the digital chip, wherein the digital chip is electrically connected to the first redistribution layer;
a molding compound over the digital chip;
a radio frequency chip over the molding compound;
a second redistribution layer adjacent the radio frequency chip, wherein the radio frequency chip is electrically connected to the second redistribution layer; and
an isolation layer in the molding compound and between the digital chip and the radio frequency chip,
wherein the molding compound encloses the digital chip and the radio frequency chip.

2. The package of claim 1 , wherein the isolation layer is formed over the digital chip and adjacent to the digital chip.

3. The package of claim 2 , wherein the isolation layer is a metallization layer.

4. The package of claim 3 , wherein the metallization layer is formed by chemical vapor deposition over the radio frequency chip.

5. The package of claim 3 , wherein the isolation layer is formed of copper.

6. The package of claim 1 , wherein the second redistribution layer is on a side of the radio frequency chip opposite the isolation layer.

7. The package of claim 1 , wherein the digital chip and the radio frequency chip are stacked within the package.

8. The package of claim 1 , wherein the digital chip is a processor and the radio frequency chip is a radio transceiver, the package further comprising a memory chip coupled to the processor and a radio frequency power amplifier coupled to the transceiver and wherein the isolation layer is between the processor and the memory chip on one side and between the radio transceiver and the power amplifier on the other side.

9. The package of claim 1 , further comprising a plurality of interconnects between the digital chip and the radio frequency chip, wherein the interconnects bypass the isolation layer.

10. The package of claim 1 , wherein the first redistribution layer comprises a package substrate to which the cover is attached, the package substrate being directly attached to the digital chip.

11. The package of claim 10 , further comprising a ground plane connection from the isolation layer to the substrate.

12. A method comprising:
placing a digital chip over a first redistribution layer so that the digital chip is adjacent to and electrically connected to the first redistribution layer;
placing a radio frequency chip over a second redistribution layer so that the digital chip is adjacent to and electrically connected to the second redistribution layer;
forming an isolation layer over the digital chip;
applying a molding compound over the digital chip and the isolation layer;
placing the radio frequency chip and the second redistribution layer over the molding compound,
wherein the molding compound encloses the digital chip and the radio frequency chip to form a package.

13. The method of claim 12 , wherein placing the digital chip comprises placing the digital chip over a carrier, the method further comprising removing the carrier after forming the isolation area.

14. The method of claim 12 , further comprising forming the first redistribution layer after forming the isolation layer to connect the digital chip to external components.

15. A computing system comprising:
a user interface controller;
an antenna; and
a multiple chip package having a digital chip coupled to the user interface controller, a first redistribution layer adjacent the digital chip electrically connected to the digital chip, a molding compound over the digital chip, a radio frequency chip, coupled to the antenna over the molding compound, a second redistribution layer adjacent the radio frequency chip electrically connected to the radio frequency chip, an isolation layer in the molding compound between the digital chip and the radio frequency chip, wherein the molding compound encloses the digital chip and the radio frequency chip.

16. The computing system of claim 15 , wherein the isolation layer is a metallization layer formed over the digital chip by deposition.

17. The package of claim 1 , wherein the isolation layer surrounds the digital chip.

18. The computing system of claim 15 , wherein the isolation layer surrounds the digital chip.

Assignees

• Goetz Edmund
• Memmler Bernd
• Mueller Jan-Erik
• Baumgartner Peter
• Intel Ip Corp

Inventors

• Goetz Edmund
• Memmler Bernd
• Mueller Jan-Erik
• Baumgartner Peter

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/26

  the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W90/271

  the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement · CPC title