Electro-migration enhancing method for self-forming barrier process in copper metalization

Patent metadata

Field	Value
Publication number	US-9362228-B2
Application number	US-201314059498-A
Country	US
Kind code	B2
Filing date	Oct 22, 2013
Priority date	Oct 22, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A method of forming a barrier on both the sidewalls and bottom of a via and the resulting device are provided. Embodiments include forming a metal line in a substrate; forming a Si-based insulating layer over the metal line and the substrate; forming a via in the Si-based insulating layer down to the metal line; forming a dual-layer Mn/MnN on sidewalls and a bottom surface of the via; and filling the via with metal.

First claim

What is claimed is:

1. A method comprising:
forming a metal line in a substrate;
forming a silicon-based (Si-based) insulating layer over the metal line and the substrate;
forming a via in the Si-based insulating layer down to the metal line;
forming a dual-layer of manganese (Mn)/manganese nitride (MnN) on sidewalls and a bottom surface of the via, wherein the dual layer on at least the bottom surface of the via consists of one layer of only Mn and one layer of only MnN; and
filling the via with metal.

2. The method according to claim 1 , comprising:
forming the dual-layer in situ by an atomic layer deposition (ALD) process in an ALD chamber or by a chemical vapor deposition (CVD) process in a CVD chamber.

3. The method according to claim 2 , comprising:
forming the dual-layer by depositing Mn in the ALD chamber; and
adding nitrogen-containing (N-containing) gas to the chamber during the ALD process.

4. The method according to claim 3 , wherein the N-containing gas comprises nitrogen gas (N 2 ) or ammonia (NH 3 ).

5. The method according to claim 3 , comprising forming the dual-layer at a temperature of 200° C. to 450° C.

6. The method according to claim 3 , comprising forming the dual-layer at a pressure of 0.1 Torr to 10 Torr.

7. The method according to claim 3 , comprising forming the Si-based insulating layer of silicon oxide (SiO 2 ) or an ultra-low-k (ULK) dielectric material.

8. The method according to claim 7 , wherein the MnN layer reacts with the SiO 2 or ULK dielectric material at the sidewalls of the via to form manganese silicate (MnSiO x ) to a thickness of 3 Å (angstroms) to 30 Å, and forming the Mn layer to a thickness of 3 Å to 30 Å on the MnSiO x and on the Mn layer on the bottom surface of the via.

9. The method according to claim 1 , performing a thermal anneal, wherein the Mn reacts with the Si-based insulating layer at the sidewalls of the via to form the MnSiO x barrier layer.

10. The method according to claim 1 , further comprising forming a capping layer over the metal line and substrate prior to forming the Si-based insulating layer, and forming the via through the capping layer.

11. A method comprising:
forming a metal line in a substrate;
forming a silicon-based (Si-based) insulating layer over the metal line and the substrate;
forming a via in the Si-based insulating layer down to the metal line;
depositing manganese (Mn) on sidewalls and a bottom surface of the via by atomic layer deposition (ALD) in an ALD chamber or by a chemical vapor deposition (CVD) process in a CVD chamber;
adding a nitrogen-containing (N-containing) gas to the ALD chamber during the ALD deposition to form a manganese nitride (MnN) layer to a thickness of 3 Å to 30 Å on the sidewalls and bottom surface of the via, such that a dual layer of Mn/MnN is formed, wherein the dual layer on at least the bottom surface of the via consists of one layer of only Mn and one layer of only MnN; and
performing a thermal anneal, wherein the Mn reacts with the Si-based insulating layer at the sidewalls of the via to form a Mn silicate (MnSiO x ) barrier layer to a thickness of 3 Å to 30 Å.

12. The device according to claim 11 , wherein the N-containing gas comprises nitrogen gas (N 2 ) or ammonia (NH 3 ).

13. The device according to claim 12 , comprising forming the Si-based insulating layer of silicon oxide (SiO 2 ) or an ultra-low-k (ULK) dielectric material.

Assignees

• Globalfoundries Inc

Inventors

• Chae Moosung
• Zhao Larry

Classifications

• H10W20/0552

  by diffusing metallic dopants to react with dielectrics · CPC title

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/076

  in via holes or trenches · CPC title

• H10W20/047

  by introducing additional elements therein · CPC title