Polishing with eddy current feed meaurement prior to deposition of conductive layer

Patent metadata

Field	Value
Publication number	US-9362186-B2
Application number	US-201514800246-A
Country	US
Kind code	B2
Filing date	Jul 15, 2015
Priority date	Jul 18, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A method of controlling polishing includes storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of a conductive layer over the at least one layer, after deposition of the conductive layer over the at least one layer and during polishing of the conductive layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ eddy current monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

First claim

What is claimed is:

1. A computer program product, encoded on one or more non-transitory computer storage media, comprising instructions that when executed by one or more computers cause the one or more computers to perform operations comprising:
storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of a conductive layer over the at least one layer;
after deposition of the conductive layer over the at least one layer and during polishing of the conductive layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ eddy current monitoring system;
normalizing each raw measurement in the sequence of raw measurements to generate a sequence of normalized measurements using the raw measurement and the base measurement; and
determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

2. The computer program product of claim 1 , wherein the at least one layer overlying the semiconductor wafer comprises an underlying conductive layer and a dielectric layer overlaying the underlying conductive layer.

3. The computer program product of claim 2 , wherein the base measurement comprises a measurement of the substrate after deposition of the dielectric layer but before an etching process of the dielectric layer.

4. The computer program product of claim 2 , wherein the base measurement comprises a measurement of the substrate after an etching process of the dielectric layer but before deposition of a nitride layer over the dielectric layer.

5. The computer program product of claim 2 , wherein the base measurement comprises a measurement of the substrate after deposition of a nitride layer over the dielectric layer but before depositing the conductive layer to undergo polishing.

6. The computer program product of claim 1 , wherein the instructions to perform normalizing comprise instructions to perform a division operation in which the raw measurement is in a numerator and the base measurement is in a denominator.

7. The computer program product of claim 6 , wherein the division operation comprises calculating

R
=

A
-

D
A

B
-

D
B

where R is the normalized measurement, A is the raw measurement, B is the base measurement and D A and D B are measurements made by the in-situ eddy current monitoring system when no substrate is being measured by the in-situ eddy current monitoring system.

8. The computer program product of claim 1 , wherein the operations further comprise generating a sequence of values from the sequence of measurements, fitting a function to the sequence of values, determining a projected time at which the function reaches a target value, and determining at least one of the polishing endpoint or the adjustment for the polishing rate based on the projected time.

Assignees

• Applied Materials Inc

Inventors

• Kitajima Tomohiko
• David Jeffrey Drue
• Qian Jun
• Sekine Taketo
• Leung Garlen C
• Huey Sidney P

Classifications

• H10P95/062

  involving a dielectric removal step · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P72/0604

  Process monitoring, e.g. flow or thickness monitoring · CPC title