Hermetic CVD-cap with improved step coverage in high aspect ratio structures

Patent metadata

Field	Value
Publication number	US-9362111-B2
Application number	US-201514609129-A
Country	US
Kind code	B2
Filing date	Jan 29, 2015
Priority date	Feb 18, 2014
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Implementations described herein generally relate to methods for forming dielectric films in high aspect ratio features. In one implementation, a method for forming a silicon oxide layer is provided. A silicon-containing precursor gas is flown into a processing chamber having a substrate having a high aspect ratio feature disposed therein. Then a high frequency plasma is applied to the silicon-containing precursor gas to deposit a silicon-containing layer over the surface of the high aspect ratio feature. The processing chamber is purged to remove by-products from the silicon-containing layer deposition process. An oxygen-containing precursor gas is flown into the processing chamber. A high frequency plasma and a low frequency plasma are applied to the oxygen-containing precursor gas to form the silicon oxide layer.

First claim

The invention claimed is:

1. A method for forming a silicon oxide liner layer in a feature, sequentially comprising:
forming a bulk silicon oxide layer over a high aspect ratio feature formed in a substrate;
flowing a silicon-containing precursor gas into a processing region having the substrate disposed therein;
applying a high frequency plasma to the silicon-containing precursor gas;
depositing a silicon-containing layer over the surface of the bulk silicon oxide layer;
optionally purging the processing region;
flowing an oxygen-containing precursor gas into the processing chamber;
applying the high frequency plasma and a low frequency plasma to the oxygen-containing precursor gas; and
reacting the energized oxygen-containing precursor gas with the deposited silicon-containing layer to form a silicon oxide capping layer on the bulk silicon oxide layer, wherein the bulk silicon oxide layer and the silicon oxide capping layer are formed using different methods, and wherein the silicon oxide liner layer includes the bulk silicon oxide layer and the silicon oxide capping layer.

2. The method of claim 1 , wherein applying the high frequency plasma to the silicon-containing precursor gas further comprises applying a low-frequency plasma to the silicon-containing precursor gas.

3. The method of claim 1 , wherein the silicon-containing precursor gas is selected from the group consisting of: dimethylsilane, trimethylsilane, tetramethylsilane, diethylsilane, tetramethylorthosilicate (TMOS), tetraethylorthosilicate (TEOS), octamethyltrisiloxane (OMTS), octamethylcyclotetrasiloxane (OMCTS), tetramethyldimethyldimethoxydisilane, tetramethylcyclotetrasiloxane (TOMCATS), dimethyl dimethoxy silane (DMDMOS), diethoxymethyl silane (DEMS), triethoxysilane (TES), methyl triethoxysilane (MTES), phenyldimethylsilane, phenylsilane and combinations thereof.

4. The method of claim 3 , wherein the oxygen-containing precursor gas is selected from the group consisting of: molecular oxygen (O 2 ), ozone (O 3 ), NO, NO 2 , N 2 O, H 2 O, H 2 O 2 , CO, CO 2 and combinations thereof.

5. The method of claim 1 , wherein the applying a high frequency plasma to the silicon-containing precursor gas and applying a high frequency plasma and a low frequency plasma to the oxygen-containing precursor gas are performed in-situ in the processing chamber.

6. The method of claim 1 , wherein the silicon-containing precursor gas is TEOS and the oxygen-containing precursor gas is oxygen.

7. The method of claim 1 , wherein a thickness of the silicon oxide liner layer is between about 30 nanometers to about 1 micrometer.

8. The method of claim 1 , wherein the feature is at least one of: a via, a trench, a line, a contact hole, a through-hole, or combinations thereof.

9. The method of claim 1 , further comprising depositing a metallic conductor over the silicon oxide liner layer.

10. The method of claim 1 , wherein a temperature of the substrate is between 350 degrees Celsius and 450 degrees Celsius during the process of forming the silicon oxide capping layer in the feature.

11. The method of claim 1 , wherein a pressure in the processing region is between 2 Torr and 8 Torr during the process of forming the silicon oxide liner layer in the feature.

12. The method of claim 1 , wherein the high frequency plasma is maintained by applying a current at a frequency of about 13.56 MHz at a power level of from about 200 watts to about 400 watts.

13. The method of claim 1 , wherein the low frequency plasma is maintained by applying a current at a frequency of about 350 kHz at a power level from about 200 watts to about 400 watts.

14. A method of forming a through-silicon via, comprising:
etching a plurality of vias in a silicon substrate, the vias each having a sidewall and a bottom wall;
forming a silicon oxide liner layer on the sidewall and the bottom wall of each of the plurality of vias by:
forming a bulk silicon oxide layer on the sidewall and the bottom wall of each of the plurality of vias;
flowing a silicon-containing precursor gas into a processing region having the silicon substrate disposed therein, wherein the silicon-containing precursor gas comprises a Si—O bond;
applying a high frequency plasma to the silicon-containing precursor gas;
depositing a silicon-containing layer on the surface of the bulk silicon oxide layer;
optionally purging the processing region;
flowing an oxygen-containing precursor gas into the processing chamber; and
applying a high frequency plasma and a low frequency plasma to the oxygen-containing precursor gas to form the silicon oxide capping layer on the bulk silicon oxide layer, wherein the bulk silicon oxide layer and the silicon oxide capping layer are formed using different methods, and wherein the silicon oxide liner layer includes the bulk silicon oxide layer and the silicon oxide capping layer; and

depositing a metallic conductor over the silicon oxide liner layer.

15. The method of claim 14 , wherein the silicon-containing precursor gas is tetraethylorthosilicate (TEOS) and the oxygen-containing precursor gas is oxygen (O 2 ).

16. The method of claim 14 , wherein a temperature of the substrate is between 350 degrees Celsius and 450 degrees Celsius during the process of forming the silicon oxide capping layer.

17. The method of claim 14 , wherein a pressure in the processing region is between 2 Torr and 8 Torr during the process of forming the silicon oxide capping layer.

18. The method of claim 14 , wherein the high frequency plasma is maintained by applying a current at a frequency of about 13.56 MHz at a power level of from about 200 watts to about 400 watts.

19. The method of claim 14 , wherein the low frequency plasma is maintained by applying a current at a frequency of about 350 kHz at a power level from about 200 watts to about 400 watts.

20. The method of claim 14 , further comprising, after depositing the metallic conductor in the vias, flipping the silicon substrate over and chemical mechanical polishing a back surface of the substrate to expose top portions of the metallic conductor deposited into the vias of the silicon substrate.

Assignees

• Applied Materials Inc

Inventors

• Wang Zongbin
• Sudheeran Shalina Deepa
• Sundarrajan Arvind
• Bhushan Bharat

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P52/402

  of semiconductor materials · CPC title

• H10P14/69215

  the material being a silicon oxide, e.g. SiO2 · CPC title