Temperature compensation method for high-density floating-gate memory
US-2015008496-A1 · Jan 8, 2015 · US
Memory cell capable of operating under low voltage conditions
US9362001B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9362001-B2 |
| Application number | US-201514798478-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 14, 2015 |
| Priority date | Oct 14, 2014 |
| Publication date | Jun 7, 2016 |
| Grant date | Jun 7, 2016 |
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Abstract
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A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be operated in the beginning of the reading operation of the memory cell so that the window of time for reading data from the memory cell can be widened.
First claim
Opening claim text (preview).
What is claimed is: 1. A memory cell comprising: a programming selection transistor having a first terminal, a second terminal configured to receive a bit line program signal, and a control terminal configured to receive a word line program signal; a following gate transistor having a first terminal, a second terminal coupled to the first terminal of the programming selection transistor, and a control terminal configured to receive a following control signal; an antifuse eleme…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9362001B2 cover?
- A memory cell includes a programming selection transistor, a following gate transistor, an antifuse element, and a reading circuit. A charging current formed by the antifuse element may trigger the reading circuit to form a stable read current during a reading operation of the memory cell so that the time for reading data from the memory cell can be shortened. A discharging process may be opera…
- Who is the assignee on this patent?
- Ememory Technology Inc
- What technology area does this patent fall under?
- Primary CPC classification G11C17/18. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Tue Jun 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).