Apparatuses including cross point memory arrays and biasing schemes

Patent metadata

Field	Value
Publication number	US-9361979-B2
Application number	US-201514702330-A
Country	US
Kind code	B2
Filing date	May 1, 2015
Priority date	Jun 23, 2009
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Memory devices comprise a plurality of memory cells, each memory cell including a memory element and a selection device. A plurality of first (e.g., row) address lines can be adjacent (e.g., under) a first side of at least some cells of the plurality. A plurality of second (e.g., column) address lines extend across the plurality of row address lines, each column address line being adjacent (e.g., over) a second, opposing side of at least some of the cells. Control circuitry can be configured to selectively apply a read voltage or a write voltage substantially simultaneously to the address lines. Systems including such memory devices and methods of accessing a plurality of cells at least substantially simultaneously are also disclosed.

First claim

What is claimed is:

1. An apparatus, comprising:
a three-dimensional array of cross-point memory cells, including:
a first set of address lines extending in a first direction;
a second set of address lines extending in a second direction transverse to the first direction, wherein pairs of adjacent intersections of the first set and the second set define at least one memory cell between them, and wherein:
a first plurality of memory cells is located between a first address line of the first set of address lines and the second set of address lines in a first plane; and
a second plurality of memory cells is located between the second set of address lines and a second address line of the first set of address lines in a second plane; and

control circuitry configured to bias the first set of address lines and the second set of address lines according to a bias scheme that causes at least one memory cell of the first plurality of memory cells in the first plane and at least one memory cell of the second plurality of memory cells in the second plane to have a same data value accessed within a single clock cycle while at least one other memory cell of the first plurality of memory cells in the first plane and at least one other memory cell of the second plurality of memory cells in the second plane are not accessed within the single clock cycle.

2. The apparatus of claim 1 , wherein each memory cell of the first and second pluralities of memory cells includes a memory element coupled to a selection device, and is configured to store a first data value therein if a positive voltage is across the respective memory cell, and to store a second data value therein if a negative voltage is across the respective memory cell.

3. The apparatus of claim 1 , wherein the three-dimensional array of cross-point memory cells is implemented as one of a magnetoresistive random access memory (MRAM) device, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM), or a phase change random access memory (PCRAM) device.

4. The apparatus of claim 1 , wherein the first plurality of address lines are row address lines, and the second plurality of address lines are column address lines, and wherein the control circuitry includes:
row decode/enable circuitry configured to provide a respective voltage to each row address line; and
column decode/enable circuitry configured to provide a respective voltage to each column address line.

5. The apparatus of claim 1 , wherein the bias scheme includes the control circuitry:
applying a write voltage to the first address line of the first set of address lines;
applying a reference voltage to the second address line of the first set of address lines;
applying the write voltage to at least one address line of the second set of address lines; and
applying the reference voltage to at least one additional address line of the second set of address lines.

6. The apparatus of claim 1 , further comprising a memory device that includes the three-dimensional array of cross-point memory cells.

7. The apparatus of claim 6 , further comprising at least one input device, at least one output device, and at least one processor.

8. An apparatus, comprising:
a three-dimensional array of cross-point memory cells, including:
a first address line coupled to a first side of a first plurality of memory cells in a first plane;
a second address line coupled to a first side of a second plurality of memory cells in a second plane;
a first plurality of intersecting address lines extending across, and between, the first address line and the second address line, wherein:
each intersecting address line of the first plurality of intersecting address lines is coupled to a second side of a memory cell of the first plurality of memory cells; and
each intersecting address line of the first plurality of intersecting address lines is coupled to a second side of a memory cell of the second plurality of memory cells; and

control circuitry configured to selectively bias the first address line, the second address line, and the first plurality of intersecting address lines according to a bias scheme such that at least two memory cells in different planes are accessed having a same data value during a same clock cycle.

9. The apparatus of claim 8 , wherein the bias scheme includes the control circuitry:
selectively applying a reference voltage to the first address line;
selectively applying a write voltage to the second address line; and
selectively applying a combination of either the write voltage, the reference voltage, or an intermediate voltage to the different intersecting address lines of the first plurality of intersecting address lines during the same clock cycle, wherein the intermediate voltage is a voltage between the write voltage and the reference voltage.

10. The apparatus of claim 9 , wherein the bias scheme includes the control circuitry:
selectively applying the write voltage to the first address line;
selectively applying the reference voltage to the second address line; and
selectively applying the combination of either the write voltage, the reference voltage, or the intermediate voltage to the different intersecting address lines of the first plurality of intersecting address lines during a subsequent clock cycle.

11. The apparatus of claim 8 , wherein the second address line is coupled to a first side of a third plurality of memory cells in a third plane, and wherein the three-dimensional array of cross-point memory cells further includes:
a third address line coupled to a first side of a fourth plurality of memory cells in a fourth plane; and
a second plurality of intersecting address lines extending across, and between, the second address line and the third address line, wherein:
each intersecting address line of the second plurality of intersecting address lines is coupled to a second side of a memory cell of the third plurality of memory cells; and
each intersecting address line of the second plurality of intersecting address lines is coupled to a second side of a memory cell of the fourth plurality of memory cells.

12. The apparatus of claim 11 , wherein the bias scheme includes the control circuitry:
selectively applying a write voltage to the first address line;
selectively applying a reference voltage to the second address line;
selectively applying the write voltage to the third address line; and
selectively applying a combination of either the write voltage, the reference voltage, or an intermediate voltage to the different intersecting address lines of the first plurality of intersecting address lines and the second plurality of intersecting address lines during the same clock cycle, wherein the intermediate voltage is a voltage between the write voltage and the reference voltage.

13. The apparatus of claim 12 , wherein the bias scheme includes the control circuitry:
selectively applying the reference voltage to the first address line;
selectively applying the write voltage to the second address line;
selectively applying the reference voltage to the third address line; and
selectively applying a combination of either the write voltage, the reference voltage, or the intermediate voltage to the different intersecting address lines of the first plurality of intersecting address lines and the second plurality of intersecting address lines during a subsequent clock cycle.

14. The apparatus of claim 11 , wherein the bias scheme includes the control circuitry:
selectively applying an intermediate voltage to the first address line;
selectively applying a ref

Assignees

• Micron Technology Inc

Inventors

• Wells David H
• Liu Jun

Classifications

• G11C5/02 Primary

  Disposition of storage elements, e.g. in the form of a matrix array · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title

• G11C13/003

  Cell access · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C8/10

  Decoders · CPC title