Display driver integrated circuit and display data processing method thereof

Patent metadata

Field	Value
Publication number	US-9361661-B2
Application number	US-201314017422-A
Country	US
Kind code	B2
Filing date	Sep 4, 2013
Priority date	Sep 6, 2012
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A display driver integrated circuit is provided which includes a first line buffer which receives first pixel data of an odd lane in response to an external clock and outputs the first pixel data in response to an internal clock; a second line buffer which receives second pixel data of an even lane in response to the external clock and outputs the second pixel data in response to the internal clock; a line buffer controller which receives display data by the two pixel data to output the first and second pixel data; a data merger which merges the first pixel data output from the first line buffer and second pixel data output from the second line buffer; and an image data processing block which processes the merged pixel data, wherein a frequency of the internal clock is lower than a frequency of the external clock.

First claim

What is claimed is:

1. A display driver integrated circuit comprising:
a first line buffer configured to receive first pixel data of an odd lane as four pixel data in response to an external clock signal and output the first pixel data in response to an internal clock signal;
a second line buffer configured to receive second pixel data as four pixel data of an even lane in response to the external clock signal and outputs the second pixel data in response to the internal clock signal;
a line buffer controller configured to receive display data in units of two pixel data to output the first and second pixel data;
a data merger configured to merge the first pixel data output from the first line buffer and second pixel data output from the second line buffer to generate merged pixel data of a size less than or equal to the four pixel data; and
an image data processing block configured to process the merged pixel data,
wherein a frequency of the internal clock signal is lower than a frequency of the external clock signal,
wherein the two pixel data represents data for two pixels and the four pixel data represents data for four pixels.

2. The display driver integrated circuit of claim 1 , wherein the line buffer controller controls a write operation and a read operation of the first and second line buffers and uses the external clock signal as a write clock for the write operation and the internal clock signal as a read clock for the read operation.

3. The display driver integrated circuit of claim 1 , wherein the line buffer controller outputs a read data signal for merging the first pixel data output from the first line buffer and the second pixel data output from the second line buffer.

4. The display driver integrated circuit of claim 1 , wherein the image data processing block processes the merged pixel data comprising four pixel data.

5. The display driver integrated circuit of claim 4 , further comprising:
a shift register configured to shift display data, processed by the data image processing block, by the four pixel data in response to a clock signal;
a latch circuit configured to store the shifted display data; and
a source driver configured to generate an analog voltage corresponding to display data stored in the latch circuit.

6. The display driver integrated circuit of claim 1 , wherein the image data processing block processes the merged pixel data comprising the two pixel data.

7. The display driver integrated circuit of claim 6 , further comprising:
a pixel converter configured to convert two-pixel display data processed by the image data processing block into four-pixel display data.

8. The display driver integrated circuit of claim 1 , wherein the external clock signal and a data packet are received from an external device in an MIPI (mobile industry processor interface) format.

9. The display driver integrated circuit of claim 8 , further comprising:
a MIPI client configured to receive the data packet via a plurality of lanes; and
a MIPI wrapper configured to receive 32-bit display data from the MIPI client in response to the external clock signal and output 48-bit display data as a unit of the two pixel data in response to the external clock signal.

10. The display driver integrated circuit of claim 9 , wherein the plurality of lanes is 4 and a frequency of the external clock signal is below 125 MHz.

11. The display driver integrated circuit of claim 1 , further comprising:
an oscillator configured to generate the internal clock signal.

12. A display data processing method of a display driver integrated circuit, comprising:
writing first display data comprising four pixel data to a first line buffer in response to an external clock signal;
writing second display data comprising four pixel data to a second line buffer in response to an external clock signal;
reading the first display data from the first line buffer in response to an internal clock signal;
reading the second display data from the second line buffer in response to an internal clock signal;
merging the read first and second display data to generate merged data of a size less than or equal to the four pixel data; and
processing the merged data,
wherein a frequency of the internal clock signal is lower than a frequency of the external clock signal, and
wherein the four pixel data represents data for four pixels.

13. The display data processing method of claim 12 , further comprising:
receiving a data packet and the external clock signal from an external device; and
outputting the display data from the input data packet to the first line buffer and the second line buffer.

14. A display driver integrated circuit comprising:
a clock divider configured to receive an input of image data representing pixel data for a first number of pixels and output divided image data representing pixel data for a second number of pixels in response to an external clock signal;
a first-in-first-out FIFO memory configured to receive the divided image data and output the divided image data in response to an internal clock signal;
an image data processing block configured to process the divided image data output by the FIFO memory,
wherein a frequency of the internal clock signal is lower than a frequency of the external clock signal, and
wherein the second number is larger than the first number,
wherein the divided image data input to the image data processing block is four pixel data representing image data for four pixels.

15. The display driver integrated circuit of claim 14 , further comprising:
a shift register configured to shift display data output by the processing block by the four pixel data in response to a clock signal;
a latch circuit configured to store the shifted display data; and
a source driver configured to generate an analog voltage corresponding to display data stored in the latch circuit.

16. The display driver integrated circuit of claim 14 , wherein the divided image data input to the image data processing block is two pixel data representing image data for two pixels.

17. The display driver integrated circuit of claim 16 , further comprising a pixel converter configured to convert two pixel data processed by the image data processing block into four pixel data.

18. The display driver integrated circuit of claim 14 , wherein the input of image data is two pixel data representing image data for two pixels.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Bae Jong-Kon
• Kim Dokyung
• Kang Wonsik

Classifications

• G09G5/006 Primary

  Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

• G09G2370/10

  Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G09G5/399

  using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title