System on chip including unified input/output memory management unit

Patent metadata

Field	Value
Publication number	US-9361239-B2
Application number	US-201113095385-A
Country	US
Kind code	B2
Filing date	Apr 27, 2011
Priority date	Apr 28, 2010
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

A system on chip, includes a memory, a bus, a plurality of intellectual property (IP) blocks, and a unified input/output memory management unit (IOMMU) connected between the memory and the bus and configured to determine whether to perform address conversion for a transaction transferred from the bus based on transaction information.

First claim

What is claimed is:

1. A system on chip, comprising:
a central process unit (CPU) to control an overall operation of the system on chip;
a memory;
a bus including a first bus and a second bus;
a plurality of intellectual property (IP) blocks connected to the first and second buses, each of the IP blocks to generate a transaction including an intellectual property identification (IP ID) field value and a field value, the IP ID field value indicating whether the transaction from each of IP blocks is transferred through the first bus or through the second bus, the field value being used to distinguish a virtual address and a physical address and being different from the virtual address and physical address;
a unified input/output memory management unit (IOMMU) connected between the memory and the bus and to determine whether to perform address conversion for a transaction transferred from each of the IP blocks through the first bus or through the second bus based on the field value of the transferred transaction; and
a controller to generate an address translation signal for setting the field value of the transaction according to transaction state information of each of the IP blocks, the transaction state information that is provided from the CPU to the controller, wherein
the transaction state information indicates whether an address of the transaction is a virtual address or a physical address.

2. The system on chip as claimed in claim 1 , wherein the field value of the transaction is set to a value indicating that an address of the transaction is a physical address, as a default value.

3. The system on chip as claimed in claim 1 , wherein the field value of the transaction is set to a value indicating that an address of the transaction is a virtual address, based on the address translation signal.

4. The system on chip as claimed in claim 1 , wherein the unified IOMMU is to convert an address of the transferred transaction into a physical address when the field value of the transferred transaction is set to a value indicating that an address of the transaction is a virtual address.

5. The system on chip as claimed in claim 1 , wherein the unified IOMMU is to bypass the transferred transaction when the field value of the transferred transaction is set to a value indicating that an address of the transferred transaction is a physical address.

6. The system on chip as claimed in claim 1 , wherein the unified IOMMU is to judge whether address conversion is needed with respect to a next transaction during address conversion of a current transaction underway.

7. The system on chip as claimed in claim 6 , wherein when the field value of the next transaction is set to a value indicating that an address of the next transaction is a physical address, the unified IOMMU bypasses the next transaction during address conversion of the current transaction.

8. The system on chip as claimed in claim 1 , wherein the bus uses an advanced extensible interface (AXI) interface.

9. A system on chip, comprising:
a central process unit (CPU) to control an overall operation of the system on chip;
a memory;
a bus including a first bus and a second bus;
a plurality of IP blocks connected to the first and second buses, each of the IP blocks to generate a transaction to be transferred to the first bus or the second bus;
a unified input/output memory management unit (IOMMU) connected between the memory and the bus and to manage the transaction provided from the first bus or the second bus; and
a controller to provide the unified IOMMU with transaction state information indicating whether an address of the transaction is a virtual address or a physical address, wherein:
the transaction includes an intellectual property identification (IP ID) field value for discriminating the plurality of IP blocks, the IP ID field value indicating whether the transaction from each of IP blocks is transferred through the first bus or through the second bus and
the transaction state information is different from the virtual address and physical address, is provided from the CPU, and is stored in the controller.

10. The system on chip as claimed in claim 9 , wherein the unified IOMMU is to determine whether to perform address conversion with respect to the transaction, depending on transaction state information corresponding to the IP ID field value.

11. The system on chip as claimed in claim 10 , wherein when the address of the transaction is judged to be a virtual address, the unified IOMMU is to convert the address of the transaction into a corresponding physical address.

12. The system on chip as claimed in claim 10 , wherein when the address of the transaction is judged to be a physical address, the unified IOMMU is to bypass the transaction.

13. The system on chip as claimed in claim 10 , wherein the IP ID field value is defined by topology between the plurality of IP blocks and the bus.

14. The system on chip as claimed in claim 10 , wherein the unified IOMMU includes a translation look-aside buffer that stores an address translation table.

15. The system on chip as claimed in claim 14 , wherein the unified IOMMU is to convert an address based on the address translation table.

16. The system on chip as claimed in claim 14 , wherein the unified IOMMU is to read the address translation table from the memory and then convert an address for the transaction.

17. A transaction managing method of a system on chip which includes a central process unit (CPU) to control an overall operation of the system on chip, a memory and a plurality of intellectual properties (IPs), the method comprising:
providing one memory management unit at an input level of the memory;
receiving a transaction output from one of the IPs through a bus including a first bus and a second bus, the first and second buses connected to the IPs, wherein
the transaction includes an intellectual property identification (IP ID) field value, the IP ID field value indicating whether the transaction from the one of IP blocks is transferred through the first bus or through the second bus, and including a field value indicating whether an address of the transaction is a virtual address or a physical address;
providing the one memory management unit with the field value;
judging whether an address conversion is to be performed based on the field value included with the transaction, the field value being different from an address;
when the transaction is judged to not include an address conversion process based on a first value of the field value, bypassing the transaction to the memory through the one memory management unit; and
when the transaction is judged to include an address conversion process based on a second value of the field value, converting an address of the transaction through the one memory management unit, wherein
the field value included with the transaction is determined according to transaction state information of the one of the IPs, and wherein
the transaction state information is provided from the CPU and indicates whether an address of the transaction is a virtual address or a physical address.

18. The transaction managing method as claimed in claim 17 , wherein the address conversion process includes converting an address of the transaction into a physical address.

19. The transaction managing method as claimed in claim 17 , wherein:
the first value of the field value indicates that the address of the transaction is a physical address, and
the second value of the field value indicate

Assignees

• Ahn Hyunsun
• Samsung Electronics Co Ltd

Inventors

• Ahn Hyunsun

Classifications

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F12/10 Primary

  Address translation · CPC title

• Y02B60/1225

  Cross-Sectional Technologies · mapped topic

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F12/04

  Addressing variable-length words or parts of words · CPC title