Adjusting a memory transfer setting with large main memory capacity

US9361226B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9361226-B2
Application numberUS-201213428969-A
CountryUS
Kind codeB2
Filing dateMar 23, 2012
Priority dateMar 23, 2012
Publication dateJun 7, 2016
Grant dateJun 7, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An apparatus for adjusting a memory transfer setting includes a storage device storing machine-readable code and a processor executing the machine-readable code. The machine-readable code includes a determination module determining that an amount of main memory exceeds a threshold percentage of secondary storage on an information handling device. The machine readable code also includes an adjustment module adjusting a memory transfer setting on the information handling device in response to the determination module determining that the amount of main memory exceeds the threshold percentage.

First claim

Opening claim text (preview).

What is claimed is: 1. An apparatus comprising: a storage device storing machine-readable code; a processor executing the machine-readable code, the machine-readable code comprising: a determination module determining that a ratio of an amount of main memory to a secondary storage for an information handling device exceeds a threshold; and an adjustment module adjusting a memory transfer setting on the information handling device in response to the determination module determining that the ratio exceeds the threshold. 2. The apparatus of claim 1 , wherein the adjustment module adjusting the memory transfer setting further comprises the adjustment module disabling a memory transfer sleep state on the information handling device, wherein the memory transfer sleep state transfers data from main memory to the secondary storage in connection with entering a sleep state. 3. The apparatus of claim 2 , wherein the adjustment module disables the memory transfer sleep state on the information handling device in the Advanced Configuration and Power Interface (“ACPI”) settings. 4. The apparatus of claim 2 , wherein the memory transfer sleep state comprises an Advanced Configuration and Power Interface (“ACPI”) S4 state. 5. The apparatus of claim 1 , wherein the adjustment module adjusting the memory transfer setting further comprises the adjustment module modifying a page file for swapping data between main memory and the secondary storage. 6. The apparatus of claim 5 , wherein the adjustment module modifies the page file by one of limiting a size of the page file and disabling the page file. 7. The apparatus of claim 1 , further comprising a reference module referencing the amount of main memory of the information handling device and one or more of the storage capacity of the secondary storage and an available storage space of the secondary storage. 8. A method comprising: determining that a ratio of an amount of main memory to a secondary storage for an information handling device exceeds a threshold; and disabling a memory transfer sleep state on the information handling device in response to determining that the ratio exceeds the threshold. 9. The method of claim 8 , wherein the memory transfer sleep state transfers data from main memory to the secondary storage in connection with entering a sleep state. 10. The method of claim 8 , wherein disabling the memory transfer sleep state further comprises disabling the memory transfer sleep state on the information handling device in the Advanced Configuration and Power Interface (“ACPI”) settings. 11. The method of claim 8 , wherein the memory transfer sleep state comprises an Advanced Configuration and Power Interface (“ACPI”) S4 state. 12. The method of claim 8 , further comprising referencing the amount of main memory of the information handling device and the storage capacity of the secondary storage of the information handling device. 13. A computer program product comprising a non-transitory computer-readable storage medium storing machine readable code executed by a processor to perform the operations of: determining that a ratio of an amount of main memory to a secondary storage for an information handling device exceeds a threshold; disabling a memory transfer sleep state on the information handling device in response to determining that the ratio of exceeds the threshold. 14. The computer program product of claim 13 , wherein the memory transfer sleep state transfers data from main memory to the secondary storage in connection with entering a sleep state. 15. The computer program product of claim 13 , wherein disabling the memory transfer sleep state further comprises disabling the memory transfer sleep state on the information handling device in the Advanced Configuration and Power Interface (“ACPI”) settings. 16. The computer program product of claim 13 , wherein the memory transfer sleep state comprises an Advanced Configuration and Power Interface (“ACPI”) S4 state.

Assignees

Inventors

Classifications

  • G06F12/08Primary

    in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

  • Addressing or allocation; Relocation (program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00) · CPC title

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What does patent US9361226B2 cover?
An apparatus for adjusting a memory transfer setting includes a storage device storing machine-readable code and a processor executing the machine-readable code. The machine-readable code includes a determination module determining that an amount of main memory exceeds a threshold percentage of secondary storage on an information handling device. The machine readable code also includes an adjus…
Who is the assignee on this patent?
Chapman Cory Allen, Keown Jr William Fred, Long Jr John Edward, and 2 more
What technology area does this patent fall under?
Primary CPC classification G06F12/08. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 07 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).