Correction of block errors for a system having non-volatile memory

Patent metadata

Field	Value
Publication number	US-9361036-B2
Application number	US-201514754468-A
Country	US
Kind code	B2
Filing date	Jun 29, 2015
Priority date	Mar 14, 2013
Publication date	Jun 7, 2016
Grant date	Jun 7, 2016

Abstract

Systems and methods are disclosed for correcting block errors. In particular, a system can store a parity page per page-modulo, where a pre-determined number of pages of a block or a band of the NVM may be allocated as page-modulo XOR (“PMX”) parity pages. This enables a space efficient approach for recovering from single-block data errors.

First claim

What is claimed is:

1. A memory interface for accessing a non-volatile memory (“NVM”), the memory interface comprising control circuitry operative to:
detect whether an amount of memory currently available in the NVM is greater than a first pre-determined threshold; and
in response to detecting that the amount of memory currently available is greater than the first pre-determined threshold, allocate a pre-determined number of pages at the end of a band of the NVM as parity pages for handling read errors localized to a block of the band.

2. The memory interface of claim 1 , wherein the pre-determined number of pages is based on vendor-specific characteristics of the NVM.

3. The memory interface of claim 1 , wherein the pre-determined number of pages span across at least one stripe of the band.

4. The memory interface of claim 1 , wherein the pre-determined number of pages are located after a log table of the band.

5. The memory interface of claim 1 , wherein the control circuitry is further operative to:
detect whether the amount of memory currently available is greater than a second pre-determined threshold, wherein the second pre-determined threshold is larger than the first pre-determined threshold; and
in response to detecting that the amount of memory currently available is greater than the second pre-determined threshold, allocate a block at the end of the band as a parity block.

6. The memory interface of claim 1 , wherein the control circuitry is further operative to allocate a plurality of pages of a different band of the NVM as partial parity pages, wherein partial parities stored in the partial parity pages are used to recover from the read errors detected when the band is only partially programmed.

7. A method for allocating portions of a non-volatile memory (“NVM”) for error corrections using a memory interface through control circuitry, the method comprising:
detecting whether an amount of memory currently available in the NVM is greater than a first pre-determined threshold; and
in response to detecting that the amount of memory currently available is greater than the first pre-determined threshold, allocating a pre-determined number of pages at the end of a band of the NVM as parity pages for handling read errors localized to a block of the band.

8. The method of claim 7 , wherein the pre-determined number of pages is based on vendor specific characteristics of the NVM.

9. The method of claim 7 , wherein the pre-determined number of pages span across at least one stripe of the band.

10. The method of claim 7 , wherein the pre-determined number of pages are located after a log table of the band.

11. The method of claim 7 , wherein the second pre-determined threshold is larger than the first pre-determined threshold.

12. The method of claim 7 , wherein upon detection of available memory is greater than the second pre-determined threshold, allocate a block at the end of the band as a parity block.

13. The method of claim 7 , wherein the control circuitry may allocate a plurality of pages of a different band of the NVM as partial parity pages, wherein partial parities stored in the partial parity pages are used to recover from the read errors detected when the band is only partially programmed.

14. A system comprising:
non-volatile memory (“NVM”); and
memory interface comprising control circuitry coupled to the NVM;
means for detecting whether the amount of memory currently available in the NVM is greater than a first pre-determined threshold;
in response to detecting that the amount of memory currently available is greater than the first pre-determined threshold, means for allocating a pre-determined number of pages at the end of a band of the NVM as parity pages for handling read errors localized to a block of the band.

15. The system of claim 14 wherein the pre-determined number of pages is based on vendor-specific characteristics of the NVM.

16. The system of claim 14 wherein the pre-determined number of pages span across at least one stripe of the band.

17. The system of claim 14 wherein the pre-determined number of pages are located after a log table of the band.

18. The system of claim 14 , further comprising:
means for detecting whether the amount of available memory is greater than a second pre-determined threshold, wherein the second pre-determined threshold is larger than the first pre-determined threshold; and
in response to detecting that the amount of memory currently available is greater than the second pre-determined threshold, means for allocating a block at the end of the band as a parity block.

19. The system of claim 14 , wherein the control circuitry is further operative to allocate a plurality of pages of a different band of the NVM as partial parity pages, wherein partial parities stored in the partial parity pages are used to recover from the read errors detected when the band is only partially programmed.

Assignees

• Apple Inc

Inventors

• Vogan Andrew W
• Post Daniel J

Classifications

• G06F11/1004

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title

• G06F3/0619 Primary

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F11/1008

  in individual solid state devices (G06F11/1004 takes precedence) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F3/0631

  by allocating resources to storage systems · CPC title