Second order loop filter and multi-order delta sigma modulator including the same

US9356618B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9356618-B2
Application numberUS-201514617705-A
CountryUS
Kind codeB2
Filing dateFeb 9, 2015
Priority dateFeb 12, 2014
Publication dateMay 31, 2016
Grant dateMay 31, 2016

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  5. First independent claim

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Abstract

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Provided is a second order loop filter (LF). The second order LF includes: an operational amplifier including a first input, a second input receiving a differential input of the first input, and an output; an inverter inverting a signal output from the output of the operational amplifier to output an inverted signal; a first resistor connected to between the first input and a first node; a second resistor connected to between the output of the operational amplifier and the first node; a third resistor connected to between the first input and an input signal; a first capacitor connected to between the second input and the first node; a second capacitor connected to between the output of the operational amplifier and an output of the inverter; and a third capacitor connected to between the output and the first input of the operational amplifier, wherein the second input is connected to a ground voltage.

First claim

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What is claimed is: 1. A second order loop filter comprising: an operational amplifier comprising a first input, a second input for receiving a differential input of the first input, and an output; an inverter for inverting a signal output from the output of the operational amplifier, and outputting the inverted signal; a first resistor connected between the first input and a first node; a second resistor connected between the output of the operational amplifier and the first node; a third resistor connected between the first input and an input signal; a first capacitor connected between the second input and the first node; a second capacitor connected between the output of the operational amplifier and an output of the inverter; and a third capacitor connected between the output and the first input of the operational amplifier, wherein the second input is connected to a ground voltage. 2. The second order loop filter of claim 1 , wherein the first to third capacitors comprise variable capacitors, or the first to third resistors comprise variable resistors. 3. The second order loop filter of claim 2 , further comprising: a fourth resistor connected in parallel to the first capacitor. 4. The second order loop filter of claim 2 , wherein capacitance values of the first to third capacitors are adjusted to configure the second order LF to perform a low pass filter operation. 5. The second order loop filter of claim 3 , wherein the second or third capacitor is adjusted to configure a first order term of a denominator of a transfer function of the second order loop filter (LF) to be zero. 6. The second order loop filter of claim 2 , wherein the operational amplifier comprises an operational transconductance amplifier (OTA). 7. The second order loop filter of claim 2 , wherein the first capacitor is for adjusting a parasitic capacitance generated at the first node. 8. A second order loop filter comprising: an operational amplifier comprising a first input, a second input, a first output and a second output; a first resistor connected between the first input and a first node; a second resistor connected between the first output and the first node; a third resistor connected between the first input and a first input signal; a fourth resistor connected between the second input and a second node; a fifth resistor connected between the second output and the second node; a sixth resistor connected between the second input and a second input signal; a first capacitor connected between the first node and the second node; a second capacitor connected between the second output and the first node; a third capacitor connected between the first input and the first output; a fourth capacitor connected between the first output and the second node; and a fifth capacitor connected between the second input and the second output, wherein the first and second inputs comprise differential inputs, the first and second outputs comprise differential outputs, and the first and second input signals comprise differential input signals. 9. The second order loop filter of claim 8 , wherein the first to fifth capacitors comprise variable capacitors, or the first to sixth resistors comprise variable resistors. 10. The second order loop filter of claim 9 , further comprising: a seventh resistor connected in parallel to the first capacitor. 11. A multi-order delta-sigma modulator comprising: a second order loop filter (LF) for integrating a difference between an input signal and an analog signal, and outputting the integrated signal; a quantizer for quantizing a signal output from the second order LF, and outputting the quantized signal; and a digital to analog converter (DAC) for converting the signal output from the quantizer into an analog signal, and outputting the analog signal, wherein the second order LF comprises: an operational amplifier comprising a first input, a second input for receiving a differential input of the first input, and an output; an inverter for inverting a signal output from the output of the operational amplifier, and outputting the inverted signal; a first resistor connected between the first input and a first node; a second resistor connected between the output of the operational amplifier and the first node; a third resistor connected between the first input and an input signal; a first capacitor connected between the second input and the first node; a second capacitor connected between the output of the operational amplifier and an output of the inverter; and a third capacitor connected between the output and the first input of the operational amplifier, wherein the second input is connected to a ground voltage. 12. The multi-order delta-sigma modulator (DSM) of claim 11 , wherein the first to third capacitors comprise variable capacitors, or the first to third resistors comprise variable resistors. 13. The multi-order delta-sigma modulator (DSM) of claim 12 , further comprising: an integrator provided between the input signal and an input of the second order LF, wherein the integrator integrates a difference between the input signal and the analog signal, and transmits the integrated signal to the second order LF. 14. The multi-order delta-sigma modulator (DSM) of claim 12 , further comprising: n loop filters (LFs), wherein n is a natural number larger than zero, and wherein the n LFs and the second order LF are serially connected, and the multi-order DSM is for quantizing a final output signal from the n LFs and the second order LF that are serially connected, and outputting the quantized signal. 15. The multi-order delta-sigma modulator (DSM) of claim 12 , wherein as the n increases, a size of a noise transfer function (NFT) of the multi order DSM increases step by step.

Assignees

Inventors

Classifications

  • Analogue/digital converters using delta-sigma modulation as an intermediate step · CPC title

  • Calibration · CPC title

  • H03M3/43Primary

    the quantiser being a single bit one · CPC title

  • Leapfrog structures · CPC title

  • H03H11/126Primary

    using a single operational amplifier (H03H11/1204 takes precedence; parallel-T filters H03H11/1295) · CPC title

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What does patent US9356618B2 cover?
Provided is a second order loop filter (LF). The second order LF includes: an operational amplifier including a first input, a second input receiving a differential input of the first input, and an output; an inverter inverting a signal output from the output of the operational amplifier to output an inverted signal; a first resistor connected to between the first input and a first node; a seco…
Who is the assignee on this patent?
Korea Electronics Telecomm
What technology area does this patent fall under?
Primary CPC classification H03M3/43. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).