Relaxation oscillator with current and voltage offset cancellation

Patent metadata

Field	Value
Publication number	US-9356554-B2
Application number	US-201414329939-A
Country	US
Kind code	B2
Filing date	Jul 12, 2014
Priority date	Jul 12, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A relaxation oscillator reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current and a second current so that after the first current has been input to a first pair of circuits and the second current has been input to a second pair of circuits, the second current is input to the first pair of circuits and the first current is input to the second pair of circuits.

First claim

What is claimed is:

1. Circuitry for a relaxation oscillator, comprising:
a current swapping circuit having a first output and a second output, the current swapping circuit for sourcing a first current from the first output and a second current from the second output in response to a first logic state of a first switching signal and a second logic state of a second switching signal, and sourcing the first current from the second output and the second current from the first output in response to a second logic state of the first switching signal and a first logic state of the second switching signal;
a first current leg coupled to the first output of the current swapping circuit, the first current leg for receiving the first current when sourced from the first output and generating a first leg voltage from the first current in response to a first logic state of a third switching signal and a second logic state of a fourth switching signal, and receiving the second current when sourced from the first output and generating a second leg voltage from the second current in response to the first logic state of the third switching signal and the second logic state of the fourth switching signal;
a second current leg coupled to the second output of the current swapping circuit, the second current leg for receiving the second current when sourced from the second output and generating a third leg voltage from the second current in response to a second logic state of the third switching signal and a first logic state of the fourth switching signal, and receiving the first current when sourced from the second output and generating a fourth leg voltage from the first current in response to the second logic state of the third switching signal and the first logic state of the fourth switching signal; and
a shared current leg coupled to the first output and the second output of the current swapping circuit, the shared current leg for:
receiving the second current when sourced from the second output, and generating a first shared voltage from the second current in response to the first logic state of the third switching signal and the second logic state of the fourth switching signal;
receiving the first current when sourced from the second output, and generating a second shared voltage from the first current in response to the first logic state of the third switching signal and the second logic state of the fourth switching signal;
receiving the first current when sourced from the first output, and generating a third shared voltage from the first current in response to the second logic state of the third switching signal and the first logic state of the fourth switching signal; and
receiving the second current when sourced from the first output, and generating a fourth shared voltage from the second current in response to the second logic state of the third switching signal and the first logic state of the fourth switching signal.

2. The relaxation oscillator circuitry of claim 1 and further comprising a switching control circuit coupled to the current swapping circuit, the first current leg, the second current leg, and the shared current leg, the switching control circuit for
comparing the first leg voltage to the first shared voltage, and changing a logic state of the third switching signal and a logic state of the fourth switching signal when the first leg voltage exceeds the first shared voltage;
comparing the third leg voltage to the third shared voltage, and changing a logic state of the first switching signal, a logic state of the second switching signal, the logic state of the third switching signal, and the logic state of the fourth switching signal when the third leg voltage exceeds the third shared voltage;
comparing the second leg voltage to the second shared voltage, and changing the logic state of the third switching signal and the logic state of the fourth switching signal when the second leg voltage exceeds the second shared voltage; and
comparing the fourth leg voltage to the fourth shared voltage, and changing the logic state of the first switching signal, the logic state of the second switching signal, the logic state of the third switching signal, and the logic state of the fourth switching signal when the fourth leg voltage exceeds the fourth shared voltage.

3. The relaxation oscillator circuitry of claim 2 wherein the current swapping circuit includes:
a first current source for generating the first current;
a second current source for generating the second current;
a first switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to the first current source, and a second terminal coupled to the first output;
a second switch having a control terminal coupled to receive the first switching signal, a first terminal coupled to the second current source, and a second terminal coupled to the second output;
a third switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to the second current source, and a second terminal coupled to the first output; and
a fourth switch having a control terminal coupled to receive the second switching signal, a first terminal coupled to the first current source, and a second terminal coupled to the second output.

4. The relaxation oscillator circuitry of claim 3 wherein the first current leg includes:
a fifth switch having a control terminal coupled to receive the third switching signal, a first terminal coupled to the first output, and a second terminal;
a sixth switch having a control terminal coupled to receive the fourth switching signal, a first terminal coupled to the second terminal of the fifth switch, and a second terminal coupled to ground; and
a capacitor having a top plate coupled to the second terminal of the fifth switch, and a bottom plate coupled to ground.

5. The relaxation oscillator circuitry of claim 4 wherein the second current leg includes:
a seventh switch having a control terminal coupled to receive the fourth switching signal, a first terminal coupled to the second output, and a second terminal;
an eighth switch having a control terminal coupled to receive the third switching signal, a first terminal coupled to the second terminal of the seventh switch, and a second terminal coupled to ground; and
a capacitor having a top plate coupled to the second terminal of the seventh switch, and a bottom plate coupled to ground.

6. The relaxation oscillator circuitry of claim 5 wherein the shared current leg includes:
a ninth switch having a control terminal coupled to receive the fourth switching signal, a first terminal coupled to the first output, and a second terminal;
a tenth switch having a control terminal coupled to receive the third switching signal, a first terminal coupled to the second output, and a second terminal; and
a resistor having a first end coupled to the second terminal of the ninth switch and the second terminal of tenth switch, and a second end coupled to ground.

7. The relaxation oscillator circuitry of claim 6 wherein the switching control circuit includes a comparator having a positive input coupled to the first output, a negative input coupled to the second output, and a comparison output.

8. The relaxation oscillator circuitry of claim 7 wherein the switching control circuit further includes:
an inverter coupled to the comparison output,
a flip-flop coupled to the comparison output and the inverter; and
a frequency divider coupled to the flip-flop.

9. The relaxation oscillator circuitry of claim 7 wherein flip-flop is a RS flip-flop with an R input coupled to the inverter, an S input coupled to the comparison output, a Q output

Assignees

• Texas Instruments Inc

Inventors

• Tam Kai Yiu
• Kiaei Ali
• Haroun Baher S

Classifications

• H03B5/24

  active element in amplifier being semiconductor device (H03B5/26 takes precedence) · CPC title

• H03K3/0231

  Astable circuits {(H03K3/0315 takes precedence)} · CPC title

• H03K4/50

  in which a sawtooth voltage is produced across a capacitor · CPC title

• H03B5/04 Primary

  Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature · CPC title

• H03K4/94

  having trapezoidal shape · CPC title