Stacked gas filled surge arrester

US9356441B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9356441-B2
Application numberUS-201214346305-A
CountryUS
Kind codeB2
Filing dateSep 17, 2012
Priority dateSep 23, 2011
Publication dateMay 31, 2016
Grant dateMay 31, 2016

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

A surge arrester comprising stacked arrester units is provided that is that is easy to assemble. For that, a surge arrester comprises stacked arrester units, a capacitor, and a resilient element, where the resilient element electrically and mechanically connects the capacitor with a node of the arrester stack.

First claim

Opening claim text (preview).

The invention claimed is: 1. A surge arrester (SAR), comprising a first terminal (T 1 ), a first node (N 1 ) and a second terminal (T 2 ), an input arrester unit (AU 0 ) and a first arrester unit (AU 1 ), a first capacitor (CA 1 ), and a first resilient element (RE 1 ), a first connection element (CE 1 ), a second connection element (CE 2 ) for connecting the surge arrester with an external circuit and a circuit board (CB) having a first side, where the first node (N 1 ) is arranged between the first terminal (T 1 ) and the second terminal (T 2 ), the input arrester unit (AU 0 ) is electrically connected between the first terminal (T 1 ) and the first node (N 1 ), the first arrester unit (AU 1 ) is electrically connected between the first node (N 1 ) and the second terminal (N 2 ), the first capacitor (CA 1 ) is electrically connected between the first terminal (T 1 ) and the first node (N 1 ), the first resilient element (RE 1 ) establishes a mechanical and an electrical connection between the first capacitor (CA 1 ) and the first node (N 1 ), where the arrester units (AU 0 , AU 1 ) are arranged between the connection elements (CE 1 , CE 2 ), the connection elements (CE 1 , CE 2 ) are electrically connected to the first (T 1 ) and second (T 2 ) terminal respectively, the circuit board (CB) is arranged between the connection elements (CE 1 , CE 2 ), the first capacitor (CA 1 ) is arranged on the first side of the circuit board (CB), the first resilient element (RE 1 ) is a metal clip (CL) mechanically connecting the circuit board (CB) with the first node (N 1 ). 2. The surge arrester of claim 1 , comprising the input arrester unit (AU 0 ), n arrester units (AU 1 , SAU 2 , . . . ), n capacitors (CA 1 , CA 2 , . . . ), n Nodes (N 1 , N 2 , . . . ) and n resilient elements (RE 1 , RE 2 , . . . ), where in the n-th stage the n-th resilient element (REn) establishes a mechanical and electrical connection between the n-th capacitor (CAn) and the n-th node (Nn), and n=2, 3, 4, 5, or more. 3. The surge arrester of claim 2 , where each arrester unit (AU 0 , AU 1 , . . . ) comprises a gas filled surge arrester, each resilient element (RE 1 , RE 2 , . . . ) comprises a U-shaped distal end (U) for a mechanical connection between the circuit board (CB) and the respective node (N 1 , N 2 , . . . ), and a lever (LE) for exerting a force onto the respective node (N 1 , N 2 , . . . ). 4. The surge arrester of claim 3 , comprising a fuse (FU) being arranged on the first side of the circuit board (CB) and being electrically connected between the first terminal (TE) and the capacitors (CA 1 , CA 2 , . . . ). 5. The surge arrester of claim 3 , comprising a conductor being arranged on the first side of the circuit board (CB) and being electrically connected between the first terminal (TE) and the capacitors (CA 1 , CA 2 , . . . ). 6. The surge arrester of claim 5 , where the capacitors (CA 1 , CA 2 , . . . ) are SMD-capacitors. 7. The surge arrester of claim 6 , where each capacitor (CA 1 , CA 2 , . . . ) has a capacity between 50 and 150 pF and each stacked arrester unit has an arc voltage between 10 and 30 V. 8. The surge arrester of claim 1 , further comprising electrodes (EL) between the arrester units (AU 0 , AU 1 , . . . ), where the electrodes (EL) have a flat side (FS) for contacting the resilient element (RE 1 ). 9. The surge arrester of claim 1 , where the first terminal and second terminal are braze welded to the respective arrester units, and the connection elements are braze weldable to an external circuit board. 10. A method for manufacturing the surge arrester (SAR) of claim 1 , comprising the steps providing a stack of arrester units (AU 0 , AU 1 ), the stack comprising a node (N 1 ) between the arrester units (AU 0 , AU 1 ), providing a capacitor (CA 1 ) on a circuit board (CB), electrically and mechanically connecting the circuit board (CB) with the node (N 1 ) via a resilient element (RE 1 ).

Assignees

Inventors

Classifications

  • H01T4/06Primary

    Mounting arrangements for a plurality of overvoltage arresters · CPC title

  • H02H9/005Primary

    avoiding undesired transient conditions · CPC title

  • Arrangements for improving potential distribution · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US9356441B2 cover?
A surge arrester comprising stacked arrester units is provided that is that is easy to assemble. For that, a surge arrester comprises stacked arrester units, a capacitor, and a resilient element, where the resilient element electrically and mechanically connects the capacitor with a node of the arrester stack.
Who is the assignee on this patent?
Epcos Ag
What technology area does this patent fall under?
Primary CPC classification H01T4/06. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).