Semiconductor device and method of manufacturing the same
US-2024290791-A1 · Aug 29, 2024 · US
Engineered source/drain region for n-Type MOSFET
US9356136B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9356136-B2 |
| Application number | US-201313788524-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 7, 2013 |
| Priority date | Mar 7, 2013 |
| Publication date | May 31, 2016 |
| Grant date | May 31, 2016 |
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Abstract
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Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.
First claim
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The invention claimed is: 1. An integrated circuit device, comprising: a field effect transistor formed on a semiconductor body, the transistor comprising a source region and a drain region which are spaced apart from one another by a channel region in the semiconductor body, and a gate arranged over an upper planar surface of the channel region; wherein the source and drain regions comprise: a doped silicon carbide (SiC) layer having a planar bottom surface and a recessed uppe…
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Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9356136B2 cover?
- Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of th…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd, Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D30/0227. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 31 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).