Methods of forming patterns and methods of manufacturing semiconductor devices using the same

Patent metadata

Field	Value
Publication number	US-9356071-B2
Application number	US-201514804310-A
Country	US
Kind code	B2
Filing date	Jul 20, 2015
Priority date	Mar 14, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate having a gate electrode formed thereon, the gate electrode extending in a second direction;
a magnetic tunnel junction pattern overlying the gate electrode;
an insulating interlayer covering the magnetic tunnel junction pattern;
an insulation layer overlying the insulating interlayer, the insulation layer including a plurality of trenches extending in a first direction substantially perpendicular to the second direction and arranged in the second direction, the plurality of trenches comprising at least one first trench and at least one second trench, the at least one first trench comprising a first end portion and a second end portion, the at least one second trench comprising a third end portion and a fourth end portion, the first end portion of the at least one first trench corresponding to the third end portion of the at least one second trench and the second end portion of the at least one first trench corresponding to the fourth end portion of the at least one second trench, the first end portion of the at least one first trench and the third end portion of the at least one second trench being in a staggered pattern with respect to each other and/or the second end portion of the at least one trench and the fourth end portion of the at least one second trench being in the staggered pattern with respect to each other; and
a plurality of bit lines on the insulating interlayer, the plurality of bit lines respectively disposed in the plurality of trenches and electrically connected to the magnetic tunnel junction pattern, the plurality of bit lines comprising at least one first bit line and at least one second bit line; and
a plurality of third bit lines, at least one of which is coupled to that at least one first bit line, wherein a width of the at least one of the plurality of third bit lines is greater than a width of the at least one first bit line,
wherein the at least one first bit line comprises a first end portion and a second end portion, the at least one second bit line comprises a third end portion and a fourth end portion, the first end portion and the second end portion of the at least one first bit line respectively corresponds to the first end portion and the second end portion of the at least one first trench, the third end portion and the fourth end portion of the at least one second bit line respectively corresponds to the third end portion and the fourth end portion of the at least one second trench line, the first end portion of the at least one first bit line corresponds to the third end portion of the at least one second bit line and the second end portion of the at least one first bit line corresponds to the fourth end portion of the at least one second bit line.

2. The device of claim 1 , which further comprises a digit line on the substrate, the digit line extending in the second direction, the magnetic tunnel junction pattern overlapping at least a portion of the digit line.

Assignees

• Seo Bum-Seok
• Kim Ki-Joon
• Lee Kil-Ho
• Samsung Electronics Co Ltd

Inventors

• Seo Bum-Seok
• Kim Ki-Joon
• Lee Kil-Ho

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73 Primary

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10D48/40

  Devices controlled by magnetic fields · CPC title

• H01L29/82

  Electricity · mapped topic