High-voltage metal-insulator-semiconductor field effect transistor structures

Patent metadata

Field	Value
Publication number	US-9356014-B2
Application number	US-201414522652-A
Country	US
Kind code	B2
Filing date	Oct 24, 2014
Priority date	Aug 3, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.

First claim

What is claimed:

1. A high-voltage metal-insulator-semiconductor field-effect transistor structure comprising:
a field-effect transistor (FET) on a substrate in a FET region;
a high-voltage FET (HVFET) on a dielectric stack over a lightly-doped diffusion (LDD) drain in the substrate in a HVFET region, wherein the dielectric stack comprises a first insulator layer on the substrate and a first mask layer on the first insulator layer;
an NPN on the substrate in an NPN region; and
a second insulator layer contacting a portion of the first insulator layer in an area over the NPN region.

2. The structure of claim 1 , wherein:
the FET is comprised of a gate structure in the FET region; and
the HVFET comprises:
a gate structure in the HVFET region adjacent to the dielectric stack and comprised of a same material as the gate structure in the FET region; and
a raised gate structure on the dielectric stack in the HVFET region.

3. The structure of claim 1 , wherein:
the FET is comprised of a gate structure in the FET region; and
the HVFET is comprised of a raised, gate structure formed on the dielectric stack.

4. The structure of claim 1 , wherein the first insulator layer comprises an insulator layer in the first gate structure.

5. The structure of claim 1 , wherein the first mask layer comprises sidewalls of the first gate structure.

6. A high-voltage metal-insulator-semiconductor field-effect transistor structure comprising:
a field-effect transistor (FET) on a substrate in a FET region;
a high-voltage FET (HVFET) on a dielectric stack over a lightly-doped diffusion (LDD) drain in the substrate in a HVFET region; and
an NPN on the substrate in an NPN region,
wherein the dielectric stack comprises a first insulator layer on the substrate and a first mask layer on the first insulator layer; and
the HVFET comprises a second insulator layer and a first polysilicon layer over exposed surfaces of the first mask layer and the first insulator layer, wherein the second insulator layer contacts a portion of the first insulator layer in an area over the NPN region; and the second insulator layer is directly on the first mask layer in the FET region and the HVFET region.

7. The structure of claim 6 , wherein the HVFET comprises an intrinsic SiGe base on the first polysilicon layer.

8. The structure of claim 7 , wherein the HVFET comprises a third insulator layer on the polysilicon layer and the first mask layer.

9. The structure of claim 8 , wherein the forming the HVFET comprises forming a raised emitter over the third insulator layer in the portion of the HVFET region in which the first mask layer was exposed.

10. The structure of claim 1 , wherein the LDD drain is in the substrate.

11. The structure of claim 1 , wherein the dielectric stack comprises:
a first layer of a plurality of stacked dielectric layers directly on an upper surface of the LDD drain;
a second layer of the plurality of stacked dielectric layers directly on an upper surface of the first layer;
a third layer of the plurality of stacked dielectric layers directly on an upper surface of the second layer; and
a raised gate on an upper surface of the third layer.

12. The structure of claim 1 , wherein:
the FET comprises a first gate structure in the FET region;
the HVFET comprises a raised, second gate structure on the dielectric stack; and
the dielectric stack comprises:
the first insulator layer on the substrate, the first insulator layer also forming an insulator layer in the first gate structure; and
the first mask layer on the first insulator layer, the first mask layer also forming sidewalls of the first gate structure.

Assignees

• IBM
• Globalfoundries Inc

Inventors

• Clark Jr William F
• Liu Qizhi
• Pekarik John J
• Shi Yun
• Zhang Yanli

Classifications

• H10D84/121

  BJTs having built-in components · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title

• H10D64/111

  Field plates · CPC title

• H10D30/0221

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS] · CPC title

• H10D30/60

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title