Semiconductor package and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-9356002-B2
Application number	US-201514706096-A
Country	US
Kind code	B2
Filing date	May 7, 2015
Priority date	Jun 10, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A semiconductor package includes a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip, bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk, and an upper package on the lead frame and electrically connected to the lead frame.

First claim

What is claimed is:

1. A semiconductor package, comprising:
a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip;
bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip, and an uppermost surface of the bumps being substantially coplanar with an upper surface of the lower molding layer adjacent thereto;
a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps; and
an upper package on the lead frame and electrically connected to the lead frame,
wherein the lead frame includes a recessed portion that bends toward the lower substrate, a distance between the recessed portion of the lead frame on the bumps and the lower substrate being smaller than a distance between a portion of the lead frame on the lower semiconductor chip and the lower substrate.

2. The semiconductor package as claimed in claim 1 , wherein the lead frame has a thermal conductivity of about 100 W/mk to about 10,000 W/mk.

3. The semiconductor package as claimed in claim 1 , wherein the lead frame includes copper or aluminum.

4. The semiconductor package as claimed in claim 1 , wherein the uppermost surface of the bumps has a lower level than an upper surface of the lower semiconductor chip.

5. The semiconductor package as claimed in claim 1 , wherein:
the lead frame includes a lead part for power supply and a lead part for signal transmission;
the bumps include a bump for power supply and a bump for signal transmission; and
the lead part for power supply is electrically connected to the bump for power supply, and the lead part for signal transmission is electrically connected to the bump for signal transmission.

6. The semiconductor package as claimed in claim 1 , wherein:
the upper package includes connection terminals on a lower surface thereof; and
the lower package includes external terminals on a lower surface of the lower substrate, the connection terminals of the upper package having a different arrangement than the external terminals of the lower package, as viewed from a two-dimensional top viewpoint.

7. The semiconductor package as claimed in claim 6 , wherein the bumps have a non-overlapping relationship with the connection terminals and the external terminals along a vertical direction.

8. The semiconductor package as claimed in claim 6 , wherein the bumps have a different pitch along a first direction than the connection terminals along the first direction, as viewed from the two-dimensional top viewpoint, the bumps being electrically connected to corresponding connection terminals along the first direction.

9. The semiconductor package as claimed in claim 1 , further comprising a heat release part between the lower semiconductor chip and the lead frame.

10. The semiconductor package as claimed in claim 1 , further comprising a support between the lead frame and the upper package.

11. The semiconductor package as claimed in claim 1 , further comprising a passive device unit between the lower semiconductor chip and the lead frame, or between the lead frame and the upper semiconductor chip.

12. The semiconductor package as claimed in claim 1 , wherein the lower molding layer is on an upper surface of the lower substrate, the lower molding layer filling between the bumps, and between the upper surface of the lower substrate and a lower surface of the lower semiconductor chip.

13. A semiconductor package, comprising:
a lower package including a lower substrate, a lower semiconductor chip, bumps spaced apart from the lower semiconductor chip, and a lower molding layer, the lower molding layer being on a surface of the lower substrate and filling between the bumps on the surface of the lower substrate, and exposing an upper surface of the lower semiconductor chip;
a lead frame on the lower semiconductor chip and on the bumps, the lead frame being electrically connected to the bumps; and
an upper package on the lead frame and electrically connected to the lead frame,
wherein:
the lead frame includes a lead part for power supply and a lead part for signal transmission,
the bumps include a bump for power supply and a bump for signal transmission, and
the lead part for power supply is electrically connected to the bump for power supply, and the lead part for signal transmission is electrically connected to the bump for signal transmission.

14. The semiconductor package as claimed in claim 13 , wherein the lead frame includes copper or aluminum.

15. A semiconductor package, comprising:
a lower package including a lower substrate, a lower semiconductor chip, and a lower molding layer exposing an upper surface of the lower semiconductor chip;
bumps on the lower substrate, the bumps being spaced apart from the lower semiconductor chip;
a lead frame on the lower semiconductor chip and on the bumps, the lead frame including a recess that bends toward the lower substrate, and the lead frame being electrically connected to the bumps and having a thermal conductivity of about 100 W/mk to about 10,000 W/mk; and
an upper package on the lead frame and electrically connected to the lead frame, the upper package including connection terminals electrically connected to corresponding bumps via the lead frame,
wherein the connection terminals are spaced apart from the corresponding bumps along a first direction, a distance between two adjacent bumps in the first direction being different from a distance between two adjacent connection terminals in the first direction, the adjacent bumps and connection terminals being at a same side of the lower semiconductor chip.

16. The semiconductor package as claimed in claim 15 , wherein the lead frame includes a first portion and a second portion peripheral to the first portion, a distance between a bottom surface of the first portion and a bottom of the lower substrate being larger than a distance between a bottom surface of the second portion and the bottom of the lower substrate.

17. The semiconductor package as claimed in claim 15 , wherein an arrangement of the bumps in the first molding layer is different from an arrangement of external terminals on a bottom surface of the lower package, when viewed from a two-dimensional top viewpoint.

18. The semiconductor package as claimed in claim 1 , wherein the lead frame is completely external to the lower molding layer.

19. The semiconductor package as claimed in claim 1 , wherein the lead frame includes a first portion and a second portion, the first and second portions of the lead frame being electrically separated from each other to be connected to different types of bumps.

20. The semiconductor package as claimed in claim 15 , wherein:
the lead frame includes a lead part for power supply and a lead part for signal transmission;
the bumps include a bump for power supply and a bump for signal transmission; and
the lead part for power supply is electrically connected to the bump for power supply, and the lead part for signal transmission is electrically connected to the bump for signal transmission.

Assignees

• Im Yunhyeok
• Samsung Electronics Co Ltd

Inventors

• Im Yunhyeok

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/726

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title