Method of manufacturing an integrated circuit having field effect transistors including a peak in a body dopant concentration

Patent metadata

Field	Value
Publication number	US-9355909-B2
Application number	US-201414148776-A
Country	US
Kind code	B2
Filing date	Jan 7, 2014
Priority date	Mar 12, 2009
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

First claim

What is claimed is:

1. A method of forming an integrated circuit, comprising:
forming a first FET and a second FET;
electrically connecting at least one of source, drain, gate of the first FET to the corresponding one of source, drain, gate of the second FET; and
connecting at least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET to a circuit element, respectively; and
wherein the formation of the first and second FET includes forming a body of each of the first and second FETs having a dopant concentration along a channel of the respective FET that includes a peak at a peak location within the channel, and further comprising forming the first and second FETs as Trench FETs comprising trenches extending into a semiconductor substrate from a first surface of the semiconductor substrate, and wherein forming the body of each of the first and second FETs includes:
implanting dopants into the semiconductor substrate such that a peak concentration of the implanted dopants has a greater distance to the first surface than a pn junction between the source and the body.

2. The method of claim 1 , comprising forming the body of each of the first and second FETs includes:
implanting dopants into a semiconductor substrate and annealing implant damages such that a fraction of a channel area of each of the first and second FETs having a dopant concentration of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

3. The method of claim 1 , further comprising:
forming the first FET as a power FET and forming the second FET as a sense FET having an area that is smaller than the area of the power FET.

4. The method of claim 1 , further comprising:
connecting the gate of the first FET to the gate of the second FET;
connecting one of source and drain of the first FET to the corresponding one of source and drain of the second FET; and
connecting the other one of source and drain of the first FET and the other one of source and drain of the second FET to the circuit element.

5. A method, comprising:
forming a first FET and a second FET, wherein the first FET is a power FET and the second FET is a sense FET;
connecting at least one of a source, drain, or gate of the first FET to the corresponding one of a source, drain, or gate of the second FET;
connecting at least one further of the source, drain, or gate of the first FET and the corresponding one further of source, drain, or gate of the second FET to a circuit element, respectively;
wherein forming the first FET and the second FET include forming a dopant concentration profile of a body along a channel of each of the first and second FETs having a peak at a peak location within the channel, wherein a value of the dopant concentration profile of the body at the peak location of each of the first and second FETs is larger or at least equal to any value of the dopant concentration profile of the body in an extension region that extends into the source,

wherein the dopant concentration profile of the body of the first FET and the dopant concentration profile of the body of the second FET follow substantially similar contours along the channel of the first and second FETs respectively, and further comprising forming the first and second FETs as Trench FETs comprising trenches extending into a semiconductor substrate from a first surface of the semiconductor substrate, and wherein forming the body of each of die first and second FETs includes:
implanting dopants into the semiconductor substrate such that a peak concentration of the implanted dopants has a greater distance to the first surface than a pn junction between the source and the body.

6. The method of claim 5 , wherein the dopant concentration profile of the body of each of the first and second FETs is declining along the channel from the peak location to a pn junction between the body and source.

7. The method of claim 5 , wherein a fraction of a channel area of each of the first and second FETs having a dopant concentration of the body of at least 95% of a value at the peak location to an overall channel area of the respective FET is at least 15%.

8. The method of claim 5 , wherein the dopant concentration profile of the body of each of the first and second FETs has a single peak within the channel, the dopant concentration profile of the body declining to both ends of the channel in the direction of source and drain.

9. The method of claim 5 ,
wherein the gate of the first FET is connected to the gate of the second FET;
one of the source and drain of the first FET is connected to the corresponding one of the source and drain of the second FET; and
wherein the other one of the source and drain of the first FET and the other one of the source and drain of the second FET are connected to the circuit element.

10. The method of claim 5 , wherein the dopant concentration profile of the body of each of the first and second FETs continuously declines within the source.

Assignees

• Infineon Technologies Ag

Inventors

• Meyer Thorsten
• Decker Stefan
• Krischke Norbert
• Kadow Christoph

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D84/0167

  Manufacturing their channels · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title