Bitline circuits for embedded charge trap multi-time-programmable-read-only-memory

Patent metadata

Field	Value
Publication number	US-9355739-B2
Application number	US-201314084644-A
Country	US
Kind code	B2
Filing date	Nov 20, 2013
Priority date	Nov 20, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A bitline circuit for embedded Multi-Time-Read-Only-Memory including a plurality of NMOS memory cells coupled to a plurality of wordlines in each row, bitlines in each column, and a source-line. More specifically, the bitline circuit controls a charge trap behavior of the target NMOS memory array by mode-dependent bitline pull-down circuit, thereby discharging the bitline strongly to GND to trap the charge effectively in a Programming mode, and discharge the bitline weakly to GND to develop a bitline voltage to detect the charge trap state. The mode dependent circuit is realized by using at least two NMOS to switch the device strength, using a pulsed gate control in a Read mode, or using analog voltage to limit the bitline current. The proposed method further includes a protection device, allowing all bitline control circuit using thin oxide devices. The bitline circuits having mode and bank access dependent bitline circuit further enables a single device memory array, by using two arrays, wherein said one of the array is used for reference to the other array using an open bitline architecture.

First claim

What is claimed is:

1. A bitline circuit controlling a charge trap comprises a MOSFET memory array coupled to a bitline and a source-line, wherein said bitline is mode-dependent pull-down circuit changes its circuit strength causing a greater current flow through said MOSFET memory array when coupled from said source-line to said bitline, activating said mode-dependent pull-down circuit when in Programming mode and limiting said current when in Read mode, said mode-dependent pull-down circuit comprising:
a P-type MOS (PMOS) device having a source and drain coupled to a bitline high voltage (VBLH) and further connected to the bitline, and a first N-type MOS (NMOS) having said source and drain coupled to GROUND (GND), said drain connecting to said bitline, and a second NMOS having said source and drain coupled to GND and said drain further connected to said bitline, respectively, discharging said bitline to a first condition by turning on said first NMOS when in said Programming mode, and discharging to a second condition by turning on said second NMOS when in said Read mode,
wherein said first NMOS device has a size greater than that of said second NMOS device.

2. The bitline circuit recited in claim 1 further comprises a first P-type MOS (PMOS) device having a source coupled to a bitline high voltage (VBLH), and a second PMOS device having said source, drain, and gate coupled to said drain of said first PMOS, and further connected to said bitline, and further to a bitline-protection voltage (VBLH_PR) that is smaller than said VBLH by a predetermined voltage, and said first PMOS is protected when said VBLH raises when in said Programming mode.

3. The bitline circuit recited in claim 2 further comprising a first and second N-type MOS whose respective source is coupled to GROUND (GND) and a third NMOS having said source, drain, and gate coupled to the respective drain of said first and second NMOS and further connected to said bitline, and further to a voltage source (VDD), respectively discharging said bitline to a first condition by turning on said first NMOS when in said Programming mode, and respectively discharging to a second condition by turning on said second NMOS when in said Read mode, thereby protecting said first and second NMOS when said VBLH rises when in said Programming mode.

4. The bitline circuit recited in claim 1 , wherein said mode-dependent pull-down circuit comprises a P-type MOS (PMOS) having said source and drain coupled to a bitline VBLH and further connected to said bitline, and a N-type MOS (NMOS) having said source and drain coupled to GND and connected to said bitline, wherein said gate of said NMOS is controlled by said mode dependent pull-down circuit, discharging said bitline by turning on said NMOS when in said Programming mode, and periodically discharging by turning on said NMOS when in said Read mode.

5. The bitline circuit recited in claim 1 , wherein said mode-dependent pull-down circuit comprises said P-type MOS (PMOS) whose source and drain is coupled to said bitline VBLH and said bitline, and a first N-type MOS (NMOS) whose drain is coupled to said bitline, and a second NMOS whose drain, source, and gate are coupled to said source of said first NMOS, GND and further connected to an analog voltage (VREF), said bitline discharging to said first condition by turning on said first NMOS using a higher VREF when in said Programming mode, and discharging to said second condition by turning on said first NMOS using a lower voltage of VREF when in said Read mode.

6. A bitline true and complement circuit controlling a charge trap comprising a MOSFET memory array coupled to a source-line true and either true or complement bitline, and a common source-line, wherein said bitline true and complement are coupled to a respective bitline true and complement, wherein each of said bitline circuits comprises a mode dependent pull-down circuit for discharging said respective bitline, wherein said mode-dependent pull-down circuit changes a circuit strength when in Programming mode followed by a Read mode, and wherein a greater current flows through the MOS coupled to true bitline and the activated wordline from the source-line to said true bitline by activated said pull-down circuit coupling to said true bitline when in said Programming mode, and limiting said current in said both true and complement bitlines when in said Read mode, each of said mode-dependent pull-down circuit comprising a PMOS having a source and drain coupled to a bitline high voltage (VBLH) and to said bitline, and a first NMOS having said source and drain coupled to GND and to said bitline, and a second NMOS having said source and drain coupled to GND and to said bitline, respectively, wherein said second NMOS in said complement circuit is stronger than that in said true circuit, wherein discharging said true bitline to said first condition turn on said first NMOS in said true circuit while in said Programming mode, and discharging said true bitline to said second condition by turning on said second NMOS in said true circuit and said complement bitline to a third condition by turning said second NMOS in said complement circuit when in said Read mode, and
wherein said second NMOS device threshold in said complement circuit is lower than said second NMOS of said true circuit.

7. The bitline true and complement circuit recited in claim 6 , wherein said second NMOS device size of said complement circuit is greater than said second NMOS of said true circuit.

8. The bitline true and complement circuit recited in claim 6 , wherein each of said mode-dependent pull-down circuits comprises a PMOS having said source and drain coupled to said bitline high voltage (VBLH) and further connected to said bitline, and a NMOS having said source and drain coupled to GND and further to said bitline, wherein a gate of said NMOS is controlled by said mode-dependent-pull down circuit, discharging said bitline to said first condition by turning on said first NMOS when in said Programming mode, discharging said true bitline to said second condition by turning on said second NMOS for a first period in said true circuit and discharging said complement bitline to said third condition by turning on said second NMOS in said complement circuit for a second period longer than said first period when in said Read mode.

9. The bitline and complement circuit recited in claim 6 , wherein each of said mode-dependent pull-down circuit comprises a PMOS having said source and drain coupled to said bitline high voltage (VBLH) and said bitline, and a first NMOS having said drain coupled to said bitline, and said second NMOS having said drain and source coupled to said source of the first NMOS, GND, and said gate of said true circuit coupled to a first analog voltage (VREF), and said gate of said complement circuit coupled to a second analog voltage (VREF2), discharging said true bitline to said first condition by turning on said first NMOS in said true circuit using a higher voltage of VREF when in said Programming mode, and discharging said true bitline to said second condition by turning on said second NMOS in said true circuit using a lower voltage of said VREF and discharging said complement bitline to said third condition by turning on said second NMOS in said complement circuit using VREF2 when in said Read mode.

10. A bitline and complement circuit recited in claim 9 , wherein said VREF in said Read mode is lower than said VREF2.

11. An Embedded Multi-Time-Read-Only-Memory (eMTPROM) including two NMOS memory arrays, each of which is coupled to a plurality of wordlines, bitlines, and a source-line, and at least one reference wordline and bitline drivers having a mode de

Assignees

• Globalfoundries Inc

Inventors

• Castalino Pamela
• Kirihata Toshiaki
• Leu Derek H

Classifications

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C17/18 Primary

  Auxiliary circuits, e.g. for writing into memory · CPC title

• G11C11/5671 Primary

  using charge trapping in an insulator · CPC title