Storage circuit

Patent metadata

Field	Value
Publication number	US-9355687-B2
Application number	US-201414306310-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Mar 11, 2011
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit.

First claim

What is claimed is:

1. A signal processing unit comprising:
a volatile storage portion;
a first transistor;
a second transistor;
a first protective circuit;
a first wiring supplied with a first voltage;
a second wiring supplied with a second voltage;
a third wiring supplied with a clock signal; and
a fourth wiring supplied with a data signal,
wherein the volatile storage portion is electrically connected to the first wiring, the third wiring and the fourth wiring,
wherein the first protective circuit is electrically connected to the second wiring and the third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the volatile storage portion,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to the volatile storage portion,
wherein a supply of the first voltage to the first wiring is stopped after a supply of the data signal to the fourth wiring is stopped,
wherein a supply of the clock signal to the third wiring is stopped after the supply of the first voltage to the first wiring is stopped, and
wherein a supply of the second voltage to the second wiring is stopped after the supply of the clock signal to the third wiring is stopped.

2. The signal processing unit according to claim 1 , wherein the first transistor comprises a channel formation region comprising an oxide semiconductor.

3. The signal processing unit according to claim 1 , wherein the second transistor comprises a channel formation region comprising silicon.

4. The signal processing unit according to claim 1 , further comprising a capacitor,
wherein a first electrode of the capacitor is electrically connected to the gate of the second transistor.

5. The signal processing unit according to claim 1 , wherein the first protective circuit comprises a diode-connected transistor.

6. The signal processing unit according to claim 1 , further comprising a second protective circuit electrically connected to the second wiring and a gate of the first transistor.

7. The signal processing unit according to claim 1 , further comprising a third protective circuit electrically connected to the second wiring and the fourth wiring.

8. The signal processing unit according to claim 1 ,
wherein the volatile storage portion comprises an analog switch, an inverter circuit, a selector circuit and a clocked inverter circuit,
wherein the fourth wiring is electrically connected to an input terminal of the inverter circuit through the analog switch,
wherein an output terminal of the inverter circuit is electrically connected to a first input terminal of the selector circuit,
wherein an output terminal of the selector circuit is electrically connected to an input terminal of the clocked inverter circuit,
wherein an output terminal of the clocked inverter circuit is electrically connected to the input terminal of the inverter circuit,
wherein a second input terminal of the selector circuit is electrically connected to the one of the source and the drain of the second transistor, and
wherein the other of the source and the drain of the first transistor is electrically connected to the output terminal of the selector circuit.

9. A method for driving a signal processing unit comprising a volatile storage portion, a first transistor, a second transistor, a protective circuit, a first wiring supplied with a first voltage, a second wiring supplied with a second voltage, a third wiring supplied with a clock signal and a fourth wiring supplied with a data signal, wherein the volatile storage portion is electrically connected to the first wiring, the third wiring and the fourth wiring, wherein the protective circuit is electrically connected to the second wiring and the third wiring, wherein one of a source and a drain of the first transistor is electrically connected to the volatile storage portion, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, and wherein one of a source and a drain of the second transistor is electrically connected to the volatile storage portion, the method comprising the steps of:
stopping a supply of the data signal to the fourth wiring;
stopping a supply of the first voltage to the first wiring after the supply of the data signal to the fourth wiring is stopped;
stopping a supply of the clock signal to the third wiring after the supply of the first voltage to the first wiring is stopped; and
stopping a supply of the second voltage to the second wiring after the supply of the clock signal to the third wiring is stopped.

Assignees

• Semiconductor Energy Lab

Inventors

• Fujita Masashi

Classifications

• G11C29/50004

  of threshold voltage · CPC title

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C14/0054

  in which the volatile element is a SRAM cell · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• G11C14/00 Primary

  Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down · CPC title