Modifying memory permissions in a secure processing environment

Patent metadata

Field	Value
Publication number	US-9355262-B2
Application number	US-201314141941-A
Country	US
Kind code	B2
Filing date	Dec 27, 2013
Priority date	Dec 27, 2013
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Embodiments of an invention for modifying memory permissions in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to modify access permissions for a page in a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes setting new access permissions in an enclave page cache map entry. Furthermore, the page is immediately accessible from inside the secure enclave according to the new access permissions.

First claim

What is claimed is:

1. A processor comprising:
instruction hardware to receive a first instruction and a second instruction, wherein the first instruction is to extend access permissions for a page in a secure enclave and the second instruction is to be called, by an application from within the secure enclave, an operating system outside the secure enclave to invoke the second instruction to restrict access permissions for the page;
execution hardware to execute the first instruction and the second instruction, wherein execution of the first instruction and the second instruction includes changing at least one of a read, write, and execute access permission in an enclave page cache map entry without setting a modified bit in the enclave page cache map entry, wherein execution of the second instruction includes storing an enclave epoch value in the enclave page cache map entry, and wherein the page is immediately accessible from inside the secure enclave according to the changed access permissions; and
a translation lookaside buffer, wherein the operating system is to track enclave threads with translation lookaside buffer entries made stale by the changed access permissions and send interprocessor interrupts to trigger enclave thread exits and a translation lookaside buffer shootdown.

2. The processor of claim 1 , wherein the first instruction is executable from within the secure enclave.

3. The processor of claim 2 , wherein the first instruction is executable only from within the secure enclave.

4. The processor of claim 1 , wherein the second instruction is executable only in supervisor mode.

5. A method comprising:
issuing a first instruction to a hardware processor to extend access permission for a page in a secure enclave; and
executing, by the hardware processor, the first instruction, wherein execution of the first instruction includes changing at least one of a read, write, and execute access permission in an enclave page cache map entry without setting a modified bit in the enclave page cache map entry, and wherein the page is immediately accessible from inside the secure enclave according to the changed access permissions;
calling, by an application from within the secure enclave, an operating system outside the secure enclave to invoke a second instruction to restrict at least one access permission for the page;
issuing the second instruction to the hardware processor to restrict the at least one access permission for the page;
executing, by the hardware processor, the second instruction, wherein execution of the second instruction includes changing at least one of the read, write, and execute access permission in the enclave page cache map entry, and storing an enclave epoch value in the enclave page cache map entry, and wherein the page is immediately accessible from inside the secure enclave according to the changed access permissions;
tracking, by the operating system, enclave threads with translation lookaside buffer entries made stale by the changed access permissions; and
sending, by the operating system, interprocessor interrupts to trigger enclave thread exits and a translation lookaside buffer shootdown.

6. The method of claim 5 , further comprising:
accessing, by an application from within the secure enclave, the page according to the changed access permissions, and
updating, by an operating system from outside the secure enclave, page tables to reflect the changed access permissions.

7. The method of claim 5 , further comprising:
attempting, by an application from within the secure enclave, to access the page after execution of the first instruction;
determining, by the hardware processor, that a mapping for the page exists in a translation lookaside buffer; and
causing, by the hardware processor, a page fault and an asynchronous exit from the secure enclave.

8. The method of claim 7 , further comprising:
handling, by an operating system from outside the secure enclave, the page fault; and
restarting, by the operating system, the application in the secure enclave.

9. The method of claim 5 , further comprising verifying, by the application from within the secure enclave, that the changed access permissions have been set.

10. A system comprising:
a memory; and
a processor including instruction hardware to receive a first instruction and a second instruction, wherein the first instruction is to extend access permissions for a page loaded from the memory into a secure enclave and the second instruction is to be called, by an application from within the secure enclave, an operating system outside the secure enclave to invoke the second instruction to restrict access permissions for the page;
execution hardware to execute the first instruction and the second instruction, wherein execution of the first instruction and the second instruction includes changing at least one of a read, write, and execute access permission in an enclave page cache map entry without setting a modified bit in the enclave page map entry, wherein execution of the second instruction includes storing an enclave epoch value in the enclave page cache map entry, and wherein the page is immediately accessible from inside the secure enclave according to the changed access permissions; and
a translation lookaside buffer, wherein the operating system is to track enclave threads with translation lookaside buffer entries made stale by the changed access permissions and send interprocessor interrupts to trigger enclave thread exits and a translation lookaside buffer shootdown.

Assignees

• Intel Corp

Inventors

• Leslie-Hurd Rebekah
• Alexandrovich Ilya
• Anati Ittai
• Berenzon Alex
• Goldsmith Michael
• Johnson Simon
• Mckeen Francis
• Rozas Carlos
• Savagaonkar Uday
• Scarlata Vincent
• Shanbhogue Vedvyas
• Smith Wesley

Classifications

• G06F12/0875 Primary

  with dedicated cache, e.g. instruction or stack · CPC title

• G06F9/3004

  to perform operations on memory · CPC title

• G06F12/145

  the protection being virtual, e.g. for virtual blocks or segments before a translation mechanism · CPC title

• G06F21/72

  in cryptographic circuits · CPC title

• G06F21/604 Primary

  Tools and structures for managing or administering access control systems · CPC title