Performing static timing analysis in the presence of instance-based systematic variations

Patent metadata

Field	Value
Publication number	US-9355207-B2
Application number	US-201414296264-A
Country	US
Kind code	B2
Filing date	Jun 4, 2014
Priority date	Jun 4, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A method may include obtaining gate-level circuit design data that describes a gate-level circuit design. The gate-level circuit design data may include one or more instances of each of multiple cells that each may be associated with a corresponding default cell static timing data and a corresponding default cell stress data. The method may include selecting one of the instances of one of the multiple cells, determining in-design stress data associated with the selected instance, and determining whether the in-design stress data is not within a tolerance of the default cell stress data. In response to the in-design stress data not being within the tolerance of the default cell stress data, the method may include generating in-design static timing data describing a timing performance for the selected instance and updating the gate-level circuit design data such that the selected instance is associated with the in-design static timing data.

First claim

What is claimed is:

1. A method comprising:
obtaining, using a computing system, gate-level circuit design data that describes a gate-level circuit design, the gate-level circuit design data including one or more instances of each of a plurality of cells, wherein each cell of the plurality of cells is associated with a corresponding default cell static timing data, which is stored in a timing library, and a corresponding default cell stress data;
selecting, using the computing system, one of the instances of one of the plurality of cells;
determining, using the computing system, in-design stress data that describes one or more in-design stress parameters associated with the selected instance in the gate-level circuit design;
determining, using the computing system, whether the in-design stress data is not within a tolerance of the default cell stress data associated with the selected instance;
in response to the in-design stress data not being within the tolerance of the default cell stress data, the method further comprises:
generating, using the computing system, in-design static timing data describing a timing performance for the selected instance in the gate-level circuit design based on the in-design stress data of the selected instance;
appending, using the computing system, the timing library with the in-design static timing data describing the timing performance associated with the selected instance;
updating, using the computing system, the gate-level circuit design data such that the selected instance is associated with the in-design static timing data during routing of the gate-level circuit design; and
generating, using the computing system, an integrated circuit layout to fabricate an integrated circuit based on the updated gate-level circuit design data.

2. The method of claim 1 , wherein updating the gate-level circuit design data includes updating a tag in the gate-level circuit design data associated with the selected instance such that the tag is associated with the in-design static timing data in the timing library.

3. The method of claim 1 , wherein the in-design stress parameters describe physical interactions of the selected instance with one or more other instances of the one of the plurality of cells or others of the plurality of cells.

4. The method of claim 1 , wherein in response to the in-design stress data being within the tolerance of the default cell stress data, the method further comprises selecting another one of the instances of the one of the plurality of cells.

5. The method of claim 1 , wherein the default cell stress data describes one or more default stress parameters associated with the selected instance, wherein determining whether the in-design stress data is not within the tolerance of the default cell stress data includes comparing the in-design stress parameters to the default stress parameters and determining that the in-design stress parameters do not match the default stress parameters such that the in-design static timing data of the selected instance does not match the default cell static timing data of the selected instance.

6. The method of claim 1 , wherein before selecting one of the instances of one of the plurality of cells, the method further comprises:
routing the gate-level circuit design data; and
selecting a path through the routed gate-level circuit design data, wherein the selected instance of the one of the plurality of cells is selected from the selected path.

7. The method of claim 6 , further comprising determining a timing performance for one or more paths through the routed gate-level circuit design data, wherein the selected path is one of the one or more paths that is outside a specified timing tolerance based on the timing performance of the one or more paths.

8. A system comprising:
a processor; and
a non-transitory memory storing instructions that, when executed by the processor, cause the system to perform operations comprising:
obtaining gate-level circuit design data that describes a gate-level circuit design, the gate-level circuit design data including one or more instances of each of a plurality of cells, wherein each cell of the plurality of cells is associated with a corresponding default cell static timing data, which is stored in a timing library, and a corresponding default cell stress data;
selecting one of the instances of one of the plurality of cells;
determining in-design stress data that describes one or more in-design stress parameters associated with the selected instance in the gate-level circuit design;
determining whether the in-design stress data is not within a tolerance of the default cell stress data associated with the selected instance;
in response to the in-design stress data not being within the tolerance of the default cell stress data, the operations further comprise:
generate in-design static timing data describing a timing performance for the selected instance in the gate-level circuit design based on the in-design stress data of the selected instance;
appending the timing library with the in-design static timing data describing the timing performance associated with the selected instance;
updating the gate-level circuit design data such that the selected instance is associated with the in-design static timing data during routing of the gate-level circuit design and
generating an integrated circuit layout to fabricate an integrated circuit based on the updated gate-level circuit design data.

9. The system of claim 8 , wherein updating the gate-level circuit design data includes updating a tag in the gate-level circuit design data associated with the selected instance such that the tag is associated with the in-design static timing data in the timing library.

10. The system of claim 8 , wherein in response to the in-design stress data being within the tolerance of the default cell stress data, the operations further comprise selecting another one of the instances of the one of the plurality of cells.

11. The system of claim 8 , wherein the default cell stress data describes one or more default stress parameters associated with the selected instance, wherein the tolerance is met if the in-design stress parameters match the default stress parameters.

12. The system of claim 8 , wherein the default cell stress data describes one or more default stress parameters associated with the selected instance, wherein determining that the in-design stress data is not within the tolerance of the default cell stress data includes comparing the in-design stress parameters to the default stress parameters and determining that the in-design stress parameters do not match the default stress parameters such that the in-design static timing data of the selected instance does not match the default cell static timing data of the selected instance.

13. The system of claim 8 , wherein before selecting one of the instances of one of the plurality of cells, the operations further comprise:
routing the gate-level circuit design data; and
selecting a path through the routed gate-level circuit design data, wherein the selected instance of the one of the plurality of cells is selected from the selected path.

14. The system of claim 13 , wherein the operations further comprise determining a timing performance for one or more paths through the routed gate-level circuit design data, wherein the selected path is one of the one or more paths that is outside a specified timing tolerance based on the timing performance of the one or more paths.

15. A method comprising:
obtaining, using a computing system, gate-level circuit

Assignees

• Fujitsu Ltd

Inventors

• Walker William W

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/3323 Primary

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/394

  Routing (G06F30/396 takes precedence) · CPC title

• G06F17/5077

  Physics · mapped topic

• G06F17/5081 Primary

  Physics · mapped topic