System and method for automated functional coverage generation and management for IC design protocols

Patent metadata

Field	Value
Publication number	US-9355206-B2
Application number	US-201414288121-A
Country	US
Kind code	B2
Filing date	May 27, 2014
Priority date	Jan 9, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A new approach is proposed that contemplates a system and method to support automated functional coverage generation and management for an IC design protocol. The proposed approach takes advantage of table-based high-level (e.g., transaction-level) specifications of the IC design protocol, wherein the state tables are readable and easily manageable (e.g., in ASCII format) in order to automatically generate functional coverage for the IC design protocol, which include but are not limited to, coverage points, protocol transitions, and/or transaction coverage. The automatically generated functional coverage is then verified via formal verification and simulated at the register-transfer level (RTL) during the coverage generation and management process. The coverage data from the formal verification and the simulation runs are then analyzed and used to guide and revise the IC design protocol in a coverage-based closed-loop IC design process.

First claim

What is claimed is:

1. A system to support automatic functional coverage generation and management for an integrated circuit (IC) design protocol, comprising:
a specification generation engine running on a host, which in operation, is configured to automatically generate one or more specifications for functional coverage of the IC design protocol based on inputs from an architect of the IC design protocol;
a coverage validation engine running on a host, which in operation, is configured to validate the one or more specifications for the functional coverage and generate coverage data on reachable states at formal verification (FV) level;
a coverage data collection engine running on a host, which in operation, is configured to conduct simulation of the IC design protocol and collect coverage data of reached coverage points at register-transfer level (RTL); and
a coverage data analysis engine running on a host, which in operation, is configured to analyze and verify completeness of the functional coverage of the IC design protocol based on the coverage data collected at the formal verification level and at the RTL, respectively;
wherein the IC design protocol is a directory-based cache coherence protocol, which connects a plurality of System-on-Chips (SOCs) as a single multicore processor via connections among the SOCs.

2. The system of claim 1 , wherein:
each of the one or more specifications includes one or more state tables that include information related to the implementation of the IC design protocol to be shared among various phases of an IC design process.

3. The system of claim 2 , wherein:
each of the state tables is in parsable ASCII format without having any hidden states, assumptions, redundancy, or dead-ends.

4. The system of claim 1 , wherein:
the specification generation engine is configured to automatically generate a FV model for formal verification of the IC design protocol, wherein the FV model includes a formally verifiable set of files generated as a composition of one or more roles/services tables, templates, and instrumentations of the chips in the IC design protocol.

5. The system of claim 1 , wherein:
the specification generation engine is configured to automatically specify coverage properties of the IC design protocol in System Verilog Assertions (SVA) specification, which describes properties of the IC design protocol in a declarative way with an ability to be implemented both in formal verification as well as simulation.

6. The system of claim 1 , wherein:
the specification generation engine is configured to automatically generate collection points for legally defined and illegal sequences in the IC design protocol, wherein the automatically generated coverage points model and cover one or more of state coverage, transitions coverage, transaction coverage, sequence coverage and cross-coverage for the IC design protocol.

7. The system of claim 1 , wherein:
the specification generation engine is configured to automatically generate an annotated synthesizable package, which is annotated with coverage properties from the one or more specifications for RTL implementation of the IC design protocol.

8. The system of claim 1 , wherein:
the coverage data analysis engine is configured to compare the coverage data collected at the formal verification level and the RTL simulation and provide guidance to revise the simulation at the RTL.

9. The system of claim 1 , wherein:
the coverage data analysis engine is configured to compare the coverage data collected at the formal verification level and the RTL simulation and provide feedback to revise the FV model for formal verification.

10. The system of claim 1 , wherein:
the coverage data analysis engine is configured to compare the coverage data collected at the formal verification level and the RTL simulation and provide feedback to revise the one or more specifications for the functional coverage of the IC design protocol.

11. A computer-implemented method to support automatic functional coverage generation and management for an integrated circuit (IC) design protocol, comprising:
automatically generating one or more specifications for functional coverage of the IC design protocol based on inputs from an architect of the IC design protocol;
validating the one or more specifications for the functional coverage and generating coverage data on reachable states at formal verification (FV) level;
conducting simulation of the IC design protocol and collecting coverage data of reached coverage points at register-transfer level (RTL);
analyzing and verifying completeness of the functional coverage of the IC design protocol based on the coverage data collected at the formal verification level and at the RTL, respectively; and
wherein the IC design protocol is a directory-based cache coherence protocol, which connects a plurality of System-on-Chips (SOCs) as a single multicore processor via connections among the SOCs.

12. The computer-implemented method of claim 11 , further comprising:
including one or more state tables in each of the one or more specifications, wherein each of the tables includes information related to the implementation of the IC design protocol to be shared among various phases of an IC design process.

13. The computer-implemented method of claim 11 , further comprising:
automatically generating a FV model for formal verification of the IC design protocol, wherein the FV model includes a formally verifiable set of files generated as a composition of one or more roles/services tables, templates, and instrumentations of the chips in the IC design protocol.

14. The computer-implemented method of claim 11 , further comprising:
automatically specifying coverage properties of the IC design protocol in System Verilog Assertions (SVA) specification, which describes properties of the IC design protocol in a declarative way with an ability to be implemented both in formal verification as well as simulation.

15. The computer-implemented method of claim 11 , further comprising:
automatically generating collection points for legally defined and illegal sequences in the IC design protocol, wherein the automatically generated coverage points model and cover one or more of state coverage, transitions coverage, transaction coverage, sequence coverage and cross-coverage for the IC design protocol.

16. The computer-implemented method of claim 11 , further comprising:
automatically generating an annotated synthesizable package, which is annotated with coverage properties from the one or more specifications for RTL implementation of the IC design protocol.

17. The computer-implemented method of claim 11 , further comprising:
comparing the coverage data collected at the formal verification level and the RTL simulation and providing guidance to revise simulation at the RTL.

18. The computer-implemented method of claim 11 , further comprising:
comparing the coverage data collected at the formal verification level and the RTL simulation and provide feedback to revise the FV model for formal verification.

19. The computer-implemented method of claim 11 , further comprising:
comparing the coverage data collected at the formal verification level and the RTL simulation and provide feedback to revise the one or more specifications for the functional coverage of the IC design protocol.

Assignees

• Cavium Inc

Inventors

• Ikram Shahid
• Akkawi Isam
• Perveiler John
• Asher David
• Ellis James

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F15/78

  comprising a single central processing unit · CPC title

• G06F30/3323 Primary

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F11/267

  Reconfiguring circuits for testing, e.g. LSSD, partitioning · CPC title