Systems and methods for nonvolatile memory performance throttling

Patent metadata

Field	Value
Publication number	US-9355024-B2
Application number	US-201213648375-A
Country	US
Kind code	B2
Filing date	Oct 10, 2012
Priority date	Oct 10, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Systems and methods for nonvolatile memory (“NVM”) performance throttling are disclosed. Performance of an NVM system may be throttled to achieve particular data retention requirements. In particular, because higher storage temperatures tend to reduce the amount of time that data may be reliably stored in an NVM system, performance of the NVM system may be throttled to reduce system temperatures and increase data retention time.

First claim

What is claimed is:

1. A method for maximizing data retention in a memory system, the method comprising:
receiving temperature information and cycle count data associated with a portion of a nonvolatile memory (“NVM”) of the memory system from a memory of the memory system;
determining a maximum temperature for storing data in the portion of the NVM to meet a predetermined data retention target based on the retrieved temperature information and the cycle count data; and
throttling the performance of the memory system based at least in part on to the determining, wherein the throttling the performance comprises deactivating a first subset of NVM dies such that a second subset of NVM dies are not deactivated, wherein the maximum number of NVM dies in the second subset is calculated as the maximum temperature minus an environmental temperature of the memory system divided by a temperature added to the memory system by each active NVM die of the memory system.

2. The method of claim 1 , wherein throttling the performance of the memory system comprises throttling performance to keep at a system temperature one of at and below the maximum temperature.

3. The method of claim 1 , wherein throttling the performance of the memory system comprises limiting a number of NVM dies that are currently active in the memory system.

4. The method of claim 1 , wherein the temperature information and cycle count data are stored in the NVM as metadata associated with the portion of the NVM.

5. The method of claim 1 , wherein the temperature information and cycle count data are stored in a table stored in at least one of the NVM and a volatile memory of the memory system.

6. The method of claim 1 , wherein throttling the performance of the memory system begins after the portion of the NVM reaches a predetermined cycle count.

7. The method of claim 1 , wherein throttling the performance of the memory system begins after the portion of the NVM reaches a threshold uncorrectable bit error rate (“UBER”).

8. The method of claim 7 , wherein the UBER is calculated as a piecewise function of temperature and storage time.

9. The method of claim 1 , wherein the temperature information comprises temperature measurements of the portion of the NVM measured one of:
continuously;
at regular intervals; and
when the portion of the NVM is being programmed, erased, or read.

10. The method of claim 1 , wherein the temperature information is only stored when a change in temperature is measured that exceeds a predetermined threshold.

11. A nonvolatile memory (“NVM”) system, comprising:
a memory controller;
a plurality of NVM dies comprising NVM and communicatively coupled to the memory controller over a first bus;
at least one temperature sensor configured to measure a temperature of the plurality of NVM dies, wherein the memory controller is configured to throttle NVM performance by deactivating a first subset of the plurality of NVM dies based on at least one of:
the temperature of the plurality of NVM dies;
a cycle count of a portion of the NVM; and
a time elapsed since the portion of the NVM was last programmed;

wherein the memory controller is configured to calculate a maximum temperature for the NVM, and wherein the maximum temperature is a temperature at which the NVM may be stored to achieve a predetermined data retention target; and
a second subset of NVM dies that are not deactivated by the memory controller, wherein the maximum number of NVM dies in the second subset is calculated as the maximum temperature minus an environmental temperature of the NVM system divided by a temperature added to the NVM system by each active NVM die of the NVM system.

12. The NVM system of claim 11 , wherein each NVM die of the plurality of NVM dies comprises at least one of the at least one temperature sensor.

13. The NVM system of claim 11 , wherein the memory controller begins to throttle performance of the NVM when the maximum temperature corresponds to the highest temperature to which the NVM is expected to be subjected.

14. The NVM system of claim 11 , wherein the memory controller begins to throttle performance of the NVM when the portion of the NVM reaches a predetermined cycle count.

15. The NVM system of claim 11 , wherein the memory controller begins to throttle performance of the NVM when the portion of the NVM exceeds a threshold uncorrectable bit error rate (“UBER”).

16. The NVM system of claim 15 , wherein the UBER is calculated as a function of a raw bit error rate (“RBER”) and characteristics of an error checking and correction algorithm used by the NVM.

17. The NVM system of claim 11 , wherein the environmental temperature is measured with one or more of the at least one temperature sensors.

Assignees

• Apple Inc

Inventors

• Nguyen Kevin M
• Yeh David J
• Tan Cheng P
• Fai Anthony

Classifications

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F2212/7204

  Capacity control, e.g. partitioning, end-of-life degradation · CPC title