Systems, apparatuses, and methods for generating a dependency vector based on two source writemask registers

Patent metadata

Field	Value
Publication number	US-9354881-B2
Application number	US-201113992707-A
Country	US
Kind code	B2
Filing date	Dec 27, 2011
Priority date	Dec 27, 2011
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Embodiments of systems, apparatuses, and methods of performing in a computer processor dependency index vector calculation in response to an instruction that includes a first and second source writemask register operands, a destination vector register operand, and an opcode are described.

First claim

What is claimed is:

1. A method of performing in a computer processor dependency index vector calculation in response to an instruction that includes a first and second source writemask register operands, a destination vector register operand, and an opcode, the method comprising steps of:
executing the instruction to determine, for each bit position the first source writemask register, a dependence value that indicates for an iteration corresponding to that bit position, which bit position that it is dependent on;
storing the determined dependence values in corresponding data element positions of the destination vector register.

2. The method of claim 1 , wherein the destination vector register is a 128-bit vector register.

3. The method of claim 1 , wherein the destination vector register is a 256-bit vector register.

4. The method of claim 1 , wherein the destination vector register is a 512-bit vector register.

5. The method of claim 1 , wherein the source writemask registers are 16-bit registers.

6. The method of claim 1 , wherein the source writemask registers are 64-bit registers.

7. The method of claim 1 , wherein the determining and storing further comprises:
setting a counter value and a temporary value to 0;
determining if a value in the counter value bit position of the first source writemask register is 1;
when the value in the counter value bit position of the first source writemask register is 1, setting a destination vector register data element at position counter value to be the temporary value;
when the value in the counter value bit position of the first source writemask register is 0, setting a destination vector register data element at position counter value to be 0;
determining if a value in the counter value bit position of the second source writemask register is 1;
when the value in the counter value bit position of the second source writemask register is 1, setting the temporary value to be the counter value plus 1;
incrementing the counter value by 1; and
repeating the above until all necessary bit positions of the first and second source writemask registers have been processed.

8. An article of manufacture comprising:
a tangible machine-readable storage medium having stored thereon an occurrence of an instruction, wherein the instruction's format specifies as its source operands a first and second writemask register and specifies as its destination a single vector register, and wherein the instruction format includes an opcode which instructs a machine, responsive to the single occurrence of the single instruction, to determine, for each bit position of the first source writemask register, a dependence value that indicates for an iteration corresponding to that bit position, which bit position that it is dependent on, and store the determined dependence values in corresponding data element positions of the destination vector register.

9. The article of manufacture of claim 8 , wherein the destination vector register is a 128-bit vector register.

10. The article of manufacture of claim 8 , wherein the destination vector register is a 256-bit vector register.

11. The article of manufacture of claim 8 , wherein the destination vector register is a 512-bit vector register.

12. The article of manufacture of claim 8 , wherein the source writemask registers are 16-bit registers.

13. The article of manufacture of claim 8 , wherein the source writemask registers are 64-bit registers.

14. The article of manufacture of claim 8 , wherein the determining and storing further comprises:
setting a counter value and a temporary value to 0;
determining if a value in the counter value bit position of the first source writemask register is 1;
when the value in the counter value bit position of the first source writemask register is 1, setting a destination vector register data element at position counter value to be the temporary value;
when the value in the counter value bit position of the first source writemask register is 0, setting a destination vector register data element at position counter value to be 0;
determining if a value in the counter value bit position of the second source writemask register is 1;
when the value in the counter value bit position of the second source writemask register is 1, setting the temporary value to be the counter value plus 1;
incrementing the counter value by 1; and
repeating the above until all necessary bit positions of the first and second source writemask registers have been processed.

15. An apparatus comprising;
a hardware decoder to decode a single dependency index vector calculation instruction that includes a first and second source writemask register operands, a destination vector register operand, and an opcode; and
execution logic to determine, for each bit position of the first source writemask register, a dependence value that indicates for an iteration corresponding to that bit position, which bit position that it is dependent on, and store the determined dependence values in corresponding data element positions of the destination vector register.

16. The apparatus of claim 15 , wherein the destination vector register is a 128-bit vector register.

17. The apparatus of claim 15 , wherein the destination vector register is a 256-bit vector register.

18. The apparatus of claim 15 , wherein the destination vector register is a 512-bit vector register.

19. The apparatus of claim 15 , wherein the source writemask registers are either 16-bit registers or 64-bit registers.

20. The apparatus of claim 15 , wherein the execution logic to determine and store by:
setting a counter value and a temporary value to 0;
determining if a value in the counter value bit position of the first source writemask register is 1;
when the value in the counter value bit position of the first source writemask register is 1, setting a destination vector register data element at position counter value to be the temporary value;
when the value in the counter value bit position of the first source writemask register is 0, setting a destination vector register data element at position counter value to be 0;
determining if a value in the counter value bit position of the second source writemask register is 1;
when the value in the counter value bit position of the second source writemask register is 1, setting the temporary value to be the counter value plus 1;
incrementing the counter value by 1; and
repeating the above until all necessary bit positions of the first and second source writemask registers have been processed.

Assignees

• Bharadwaj Jayashankar
• Intel Corp

Inventors

• Bharadwaj Jayashankar

Classifications

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/30065

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F9/3016 Primary

  Decoding the operand specifier, e.g. specifier format · CPC title