Enhanced loop streaming detector to drive logic optimization

Patent metadata

Field	Value
Publication number	US-9354875-B2
Application number	US-201213728273-A
Country	US
Kind code	B2
Filing date	Dec 27, 2012
Priority date	Dec 27, 2012
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

An enhanced loop streaming detection mechanism is provided in a processor to reduce power consumption. The processor includes a decoder to decode instructions in a loop into micro-operations, and a loop streaming detector to detect the presence of the loop in the micro-operations. The processor also includes a loop characteristic tracker unit to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components. The processor also includes execution circuitry to execute the micro-operations in the loop with the identified hardware components disabled.

First claim

What is claimed is:

1. An apparatus comprising:
a decoder to decode instructions in a loop into micro-operations;
a loop streaming detector coupled to the decoder to detect presence of the loop in the micro-operations;
a loop characteristic tracker unit coupled to the loop streaming detector to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware components, wherein the loop characteristic tracker unit comprises a plurality of tracker bits, one or more of the tracker bits indicate whether a micro-operation of a given characteristic is in the loop;
circuitry to implement a state machine, and wherein the state machine to include a reset state where all tracker bits of the loop characteristic tracker unit are cleared, a learn state where tracker bits corresponding to the micro-operations in the loop are set, and a replay state where the micro-operations in the loop are executed with the identified hardware components disabled according to the tracker bits; and
execution circuitry coupled to the loop streaming detector to execute the micro-operations in the loop with the identified hardware components disabled.

2. The apparatus of claim 1 , further comprising an instruction decode queue coupled to an output of the decoder to store the micro-operations in the loop, wherein the identified hardware components are downstream from the instruction decode queue.

3. The apparatus of claim 1 , wherein the loop characteristic tracker unit is to disable the identified hardware components by powering down or clock gating the identified hardware components.

4. The apparatus of claim 1 , wherein the loop characteristic tracker unit is to disable one or more hardware components in an allocator and register alias table unit downstream from the decoder.

5. The apparatus of claim 1 , wherein a first subset of the identified hardware components are identified by one or more tracker bits of the loop characteristic tracker unit, the first subset of the identified hardware components include one or more of the following: logic that checks whether a micro-operation writes into one or more special-purpose registers, logic that allocates the special-purpose registers, and logic that handles a full stall condition of the special-purpose registers.

6. The apparatus of claim 5 , wherein the special-purpose registers include one or more of the following: a Floating Point Control Word (FPCW) register, a Multimedia Extensions Control and Status Register (MXCSR), and a segment register.

7. The apparatus of claim 1 , wherein a second subset of the identified hardware components are identified by one or more tracker bits of the loop characteristic tracker unit, the second subset of the identified hardware components include one or more of the following: logic that performs transactional memory operations, logic that alters a state of the transactional memory operations, and logic that performs hardware lock control.

8. The apparatus of claim 1 , wherein a third subset of the identified hardware components are identified by one or more tracker bits of the loop characteristic tracker unit, the third subset of the identified hardware components include one or more of the following: logic that detects floating point stack adjustments, and logic that tracks valid locations of the floating point stacks.

9. A method comprising:
detecting, by a processor, presence of a loop from micro-operations that are decoded by a decoder;
identifying hardware components downstream from the decoder that are not to be used by the micro-operations in the loop;
executing a state machine that includes a reset state where all tracker bits are cleared, a learn state where tracker bits corresponding to the micro-operations in the loop are set, and a replay state where the micro-operations in the loop are executed with the identified hardware components disabled according to the tracker bits; and
executing the micro-operations in the loop with the identified hardware components disabled.

10. The method of claim 9 , wherein identifying further comprises:
setting one or more tracker bits to indicate that a micro-operation of a given characteristic is in the loop; and
disabling one or more of hardware components associated with the one or more tracking bits when the tracker bit is not set.

11. The method of claim 9 , wherein disabling further comprises powering down or clock gating the identified hardware components.

12. The method of claim 9 , wherein a first subset of the identified hardware components are identified by one or more tracker bits of a loop characteristic tracker unit downstream from the decoder, the first subset of the identified hardware components include one or more of the following: logic that checks whether a micro-operation writes into one or more special-purpose registers, logic that allocates the special-purpose registers, and logic that handles a full stall condition of the special-purpose registers.

13. The method of claim 9 , wherein a second subset of the identified hardware components are identified by one or more tracker bits of a loop characteristic tracker unit downstream from the decoder, the second subset of the identified hardware components include one or more of the following: logic that performs transactional memory operations, logic that alters a state of the transactional memory operations, and logic that performs hardware lock control.

14. The method of claim 9 , wherein a third subset of the identified hardware components are identified by one or more tracker bits of a loop characteristic tracker unit downstream from the decoder, the third subset of the identified hardware components include one or more of the following: logic that detects floating point stack adjustments, and logic that tracks valid locations of the floating point stacks.

15. A system comprising:
memory; and
a processor coupled to the memory, the processor comprising one or more cores, each of the cores comprising:
a decoder to decode instructions in a loop into micro-operations;
a loop streaming detector coupled to the decoder to detect presence of the loop in the micro-operations;
a loop characteristic tracker unit coupled to the loop streaming detector to identify hardware components downstream from the decoder that are not to be used by the micro-operations in the loop, and to disable the identified hardware component, wherein the loop characteristic tracker unit comprises a plurality of tracker bits, one or more of the tracker bits indicate whether a micro-operation of a given characteristic is in the loops;
circuitry to implement a state machine, and wherein the state machine to include a reset state where all tracker bits of the loop characteristic tracker unit are cleared, a learn state where tracker bits corresponding to the micro-operations in the loop are set, and a replay state where the micro-operations in the loop are executed with the identified hardware components disabled according to the tracker bits; and
execution circuitry coupled to the loop streaming detector to execute the micro-operations in the loop with the identified hardware components disabled.

Assignees

• Merten Matthew C
• Deinlein Justin M
• Ilin Yury N
• Farcy Alexandre J
• Li Tong
• Srinivasan Srikanth T
• Intel Corp

Inventors

• Merten Matthew C
• Deinlein Justin M
• Ilin Yury N
• Farcy Alexandre J
• Li Tong
• Srinivasan Srikanth T

Classifications

• G06F9/30065 Primary

  Loop control instructions; iterative instructions, e.g. LOOP, REPEAT · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/3836

  Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution · CPC title

• G06F1/3287

  by switching off individual functional units in the computer system · CPC title