Apparatus for improving signal-to-noise performance of projected capacitance touch screens and panels

Patent metadata

Field	Value
Publication number	US-9354743-B2
Application number	US-201414254164-A
Country	US
Kind code	B2
Filing date	Apr 16, 2014
Priority date	Apr 16, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

Improved signal-to-noise performance of projected capacitance touch screens and panels is provided by an integrated circuit regulated high voltage source and high voltage/current drivers coupled to a plurality of projected capacitive touch elements that are controlled by a microcontroller. The single integrated circuit high voltage generator/driver may comprise a voltage boost circuit, a voltage reference, power-on-reset (POR), soft start, a plurality of voltage level shifters and a serial interface for coupling to the microcontroller that may control all functions related to using the projected capacitance touch screens and panels.

First claim

What is claimed is:

1. An apparatus for generating a high voltage and selectively coupling the high voltage to a plurality of nodes, comprising:
a voltage boost circuit having a high voltage output;
a voltage reference coupled to the voltage boost circuit;
a plurality of voltage level shifters/drivers, each one having a high voltage input coupled to the high voltage output of the voltage boost circuit and an independently controllable high voltage output;
logic circuits coupled to the plurality of voltage level shifters/drivers, wherein the logic circuits control the high voltage outputs thereof; and
a serial-to-parallel interface coupled to the logic circuits and the voltage boost circuit.

2. The apparatus as recited in claim 1 , further comprising a power-on-reset (POR) circuit coupled to the voltage boost circuit and the serial-to-parallel interface.

3. The apparatus as recited in claim 1 , further comprising a soft start circuit coupled to the voltage boost circuit.

4. The apparatus as recited in claim 1 , wherein the logic circuits are a plurality of AND gates.

5. The apparatus as recited in claim 4 , wherein an output enable control is coupled to an input of each one of the plurality of AND gates.

6. The apparatus as recited in claim 1 , wherein a high voltage output capacitor is coupled between the output of the voltage boost circuit and a power source common.

7. The apparatus as recited in claim 1 , wherein a boost inductor is coupled between a power input to the voltage boost circuit and a power source.

8. The apparatus as recited in claim 1 , wherein the outputs of the plurality of voltage level shifters/drivers are tri-state and having selectable output states at a power source common, the high voltage output or a high off resistance.

9. The apparatus as recited in claim 1 , wherein the serial-to-parallel interface further comprises configuration and data storage registers, wherein the configuration register stores parameters of the voltage boost circuit, and the data storage register stores output states of the plurality of voltage level shifters/drivers.

10. The apparatus as recited in claim 1 , wherein during a soft start the outputs of the plurality of voltage level shifters/drivers are disabled.

11. The apparatus as recited in claim 1 , wherein the voltage boost circuit, the voltage reference, the plurality of voltage level shifters/drivers, the logic circuits and the serial-to-parallel interface are provided in a single integrated circuit device.

12. The apparatus as recited in claim 1 , wherein the logic circuits and input circuits of the plurality of voltage level shifter/drivers comprise low voltage and low power devices.

13. The apparatus as recited in claim 1 , wherein output circuits of the plurality of voltage level shifter/drivers comprise high voltage devices having low impedance drive capabilities.

14. An method for generating a high voltage and selectively coupling the high voltage to a plurality of nodes, comprising the steps of:
coupling a voltage reference to a voltage boost circuit;
generating a high voltage by the voltage boost circuit;
coupling high voltage inputs of a plurality of voltage level shifters/drivers to a high voltage output of the voltage boost circuit, wherein the plurality of voltage level shifters/drivers each comprise an independently controllable high voltage output;
coupling logic circuits to the plurality of voltage level shifters/drivers, wherein the logic circuits control the high voltage outputs thereof; and
providing a serial-to-parallel interface coupled to the logic circuits and the voltage boost circuit.

15. The method as recited in claim 14 , further comprising: coupling a power-on-reset (POR) circuit to the voltage boost circuit and the serial-to-parallel interface.

16. The method as recited in claim 14 , wherein the logic circuits are a plurality of AND gates, the method further comprising: coupling an output enable control to an input of each one of the plurality of AND gates.

17. The method as recited in claim 14 , further comprising: coupling a high voltage output capacitor between the output of the voltage boost circuit and a power source common.

18. The method as recited in claim 14 , further comprising: coupling a boost inductor between a power input to the voltage boost circuit and a power source.

19. The method as recited in claim 14 , wherein the outputs of the plurality of voltage level shifters/drivers are tri-state and having selectable output states at a power source common, the high voltage output or a high off resistance.

20. The method as recited in claim 14 , wherein the serial-to-parallel interface further comprises configuration and data storage registers, the method further comprising: storing parameters of the voltage boost circuit and output states of the plurality of voltage level shifters/drivers in the configuration and data storage register.

21. The method as recited in claim 14 , further comprising: disabling during a soft start the outputs of the plurality of voltage level shifters/drivers.

22. The method as recited in claim 14 , wherein the logic circuits and input circuits of the plurality of voltage level shifter/drivers comprise low voltage and low power devices.

23. The method as recited in claim 14 , wherein output circuits of the plurality of voltage level shifter/drivers comprise high voltage devices having low impedance drive capabilities.

Assignees

• Microchip Tech Inc

Inventors

• Sharma Attma
• Walton Cory
• Hanauer Jerry

Classifications

• G06F3/044

  by capacitive means · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• G06F2203/04106

  Multi-sensing digitiser, i.e. digitiser using at least two different sensing technologies simultaneously or alternatively, e.g. for detecting pen and finger, for saving power or for improving position detection · CPC title

• H03K17/22

  Modifications for ensuring a predetermined initial state when the supply voltage has been applied (bi-stable generators H03K3/12) · CPC title

• G06F3/0418 Primary

  for error correction or compensation, e.g. based on parallax, calibration or alignment · CPC title