Voltage regulating circuit with selectable voltage references and method therefor

Patent metadata

Field	Value
Publication number	US-9354645-B2
Application number	US-201114115223-A
Country	US
Kind code	B2
Filing date	May 27, 2011
Priority date	May 27, 2011
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed.

First claim

The invention claimed is:

1. A voltage regulating circuit, for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level, said voltage regulating circuit comprising:
a voltage regulator and a reference level generator connected to said voltage regulator, said reference level generator being arranged to generate an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment, said voltage regulator being arranged to regulate said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level, wherein:
said reference level generator comprises an incrementer, a selection unit, and a multiplexer responsive to said selection unit;
said incrementer being arranged to generate, on the basis of said output voltage level an incremented level higher than said output voltage level;
said selection unit being arranged to select said internal reference level among two or more multiplexer input levels, said multiplexer input levels comprising at least said reference level and said incremented level; and
said multiplexer being arranged to forward said internal reference level to said voltage regulator.

2. A voltage regulating circuit comprising:
a voltage regulator including an output to provide an output voltage;
an input to receive a target reference voltage;
a reference level generator to provide an internal reference voltage, a level of said internal reference voltage based on a level of said output voltage; and
a selection unit to provide a selected one of said target reference voltage and said internal reference voltage to said voltage regulator, said selection based on a difference between said target reference voltage and said output voltage,
wherein said reference level generator comprises an incrementer arranged to generate an incremented level higher than a level of said output voltage, and said selection unit is arranged to select said incremented level as said internal reference voltage in response to said target reference voltage being higher than said incremented level; or
wherein said reference level generator further comprises a decrementer arranged to generate a decremented level lower than said output voltage and said selection unit is arranged to select said decremented level as said internal reference voltage in response to said target reference voltage being lower than said decremented level.

3. The voltage regulating circuit of claim 2 , wherein said reference level generator is arranged to generate said internal reference voltage such that said internal reference voltage does not differ from said output voltage in absolute value by more than a maximum allowed difference.

4. The voltage regulating circuit of claim 2 , wherein said selection unit is arranged to select said target reference voltage in response to said target reference voltage being lower than said incremented level.

5. The voltage regulating circuit of claim 2 , wherein said incrementer comprises an adder arranged to generate said incremented level by adding a positive increment to said level of said output voltage.

6. The voltage regulating circuit of claim 2 , wherein said selection unit is arranged to select said target reference voltage in response to said target reference voltage being lower than said incremented level but higher than said decremented level.

7. The voltage regulating circuit of claim 2 , wherein said decrementer comprises a subtractor arranged to generate said decremented level by adding a negative increment to said level of said output voltage.

8. The voltage regulating circuit of claim 2 , further comprising a feedback loop for feeding said output voltage back to said voltage regulator, said voltage regulator being arranged to vary said level of said output voltage on the basis of said level of said output voltage and said level of said internal reference voltage in order to minimize an absolute difference between said level of said output voltage and said level of said internal reference voltage.

9. The voltage regulating circuit of claim 2 , wherein said voltage regulating circuit is connected to a load, said load arranged to be powered by said output voltage.

10. An electronic device comprising the voltage regulating circuit of claim 2 , said electronic device comprising two or more loads and a voltage source for powering said loads, said loads being connected parallel, said voltage regulating circuit being connected between said voltage source and a first load of said loads so as to apply said output voltage to said first load.

11. A method comprising:
receiving a target reference voltage at a voltage regulating circuit, the voltage regulating circuit to provide an output voltage;
generating an internal reference voltage, a level of said internal reference voltage based on a level of said output voltage; and
generating said output voltage in response to selecting one of said target reference voltage and said internal reference voltage, said selection based on a difference between said target reference voltage and said output voltage
wherein generating said internal reference voltage further comprises:
generating an incremented internal reference voltage that is greater than said output voltage, and selecting said incremented internal reference voltage in response to said target reference voltage being higher than said incremented internal reference voltage; or
generating a decremented internal reference voltage that is lower than said output voltage, selecting said decremented internal reference voltage in response to said target reference voltage being lower than said decremented internal reference voltage.

12. The method of claim 11 , wherein said internal reference voltage does not differ from said output voltage in absolute value by more than a maximum allowed difference.

13. The method of claim 11 , further comprising selecting said target reference voltage in response to said target reference voltage being lower than said incremented internal reference voltage.

14. The method of claim 11 , further comprising selecting said target reference voltage in response to said target reference voltage being lower than said incremented internal reference voltage and higher than said decremented internal reference voltage.

Assignees

• Priel Michael
• Kuzmin Dan
• Sofer Sergey
• Freescale Semiconductor Inc

Inventors

• Priel Michael
• Kuzmin Dan
• Sofer Sergey

Classifications

• G05F1/563

  including two stages of regulation at least one of which is output level responsive, e.g. coarse and fine regulation · CPC title

• G05F1/465

  Internal voltage generators for integrated circuits, e.g. step down generators · CPC title

• H02M2001/0025

  Electricity · mapped topic

• G05F1/468 Primary

  characterised by reference voltage circuitry, e.g. soft start, remote shutdown · CPC title

• G05F1/56

  using semiconductor devices in series with the load as final control devices (G05F1/461 takes precedence) · CPC title