Event driven signal converters

Patent metadata

Field	Value
Publication number	US-9354611-B2
Application number	US-201414526773-A
Country	US
Kind code	B2
Filing date	Oct 29, 2014
Priority date	Oct 29, 2014
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

In some implementations, a method comprises: generating, by an event system of an integrated circuit, a first event signal in response to a clock signal; distributing the first event signal to a first digital converter, where the first event signal triggers conversion of a first analog signal to a first digital value by the first digital converter; generating, by the event system, a second event signal in response to the clock signal; and distributing the second event signal to a second digital converter, where the second event signal triggers conversion of a second analog signal to a second digital value.

First claim

What is claimed is:

1. A method comprising:
configuring a counter to increment according to a clock signal;
determining that a first count of the counter has reached a first threshold value after a first time period;
responsive to the determining that the first count of the counter has reached the first threshold value after the first time period, generating a first event signal;
distributing the first event signal to a first digital converter, where the first event signal triggers conversion of a first analog signal to a first digital signal by the first digital converter;
determining that a second count of the counter has reached a second threshold value after a second time period following the first time period;
responsive to the determining that the second count of the counter has reached the second threshold value after the second time period, generating a second event signal; and
distributing the second event signal to a second digital converter, where the second event signal triggers conversion of a second analog signal to a second digital signal.

2. The method of claim 1 , where distributing the first event signal further comprises:
gating the first event signal with an output of a 1-bit counter, the 1-bit counter having an input coupled to the first event signal.

3. A system comprising:
a first digital converter configured to convert a first analog signal to a first digital signal in response to an event signal, where the event is a count of a counter reaching a threshold value after a time period, the counter configured to count pulses of a clock signal;
a second digital converter configured to convert a second analog signal to a second digital signal in response to the event signal;
an event system configured to generate the event signal in response to an event; and
an event distribution circuit coupled to the event system and the first and second digital converters, the event distribution circuit configured to alternately provide the event signal to the first and second digital converters.

4. The system of claim 3 , where the event system generates the event signal at least two times faster than the conversion of the first or second analog signal to the first or second digital signal, respectively.

5. The system of claim 4 , further comprising:
a register programmed with the threshold value of the counter, given by

Top
=

(

t
sample

+

t
convert

)

(

2
*
TC_Clock
⁢
_Period

)

,

where t sample is a sample time, t convert is a conversion time and TC_Clock_Period is a period of the clock signal.

6. The system of claim 4 , where the first and second digital converters are analog-to-digital converters.

7. The system of claim 3 , where the event distribution circuit further comprises:
a selection circuit having an input coupled to an output of the event system, the selection circuit configured for outputting first and second logic values in response to the event signal;
a first logic coupled to the selection circuit output and the first digital converter, the first logic configured to start converting the first analog signal to the first digital signal in response to the first logic value; and
a second logic coupled to the selection circuit output and the second digital converter, the second logic configured to start converting the second analog signal to the second digital signal in response to the second logic value.

8. The system of claim 7 , where the selection circuit is a counter.

9. The system of claim 7 , where the first and second logic include at least one AND gate.

10. A circuit comprising:
a central processing unit;
first and second digital converters;
a bus coupling the central processing unit to the first and second digital converters;
an event system coupled to the central processing unit and configured to generate an event signal in response to an event and to send the event signal over an event system channel;
the first digital converter coupled to the event system and configured to convert a first analog signal to a first digital signal in response to the event signal;
the second digital converter coupled to the event system and configured to convert a second analog signal to a second digital signal in response to the event signal; and
an event distribution circuit coupled to the event system and the first and second digital converters, the event distribution circuit configured to alternately provide the event signal to the first and second digital converters.

11. The circuit of claim 10 , where the event is a count of a counter reaching a threshold value after a time period, the counter configured to count pulses of a clock signal.

12. The circuit of claim 11 , further comprising:
a register programmed with the threshold value of the counter, given by

Top
=

(

t
sample

+

t
convert

)

(

2
*
TC_Clock
⁢
_Period

)

,

where t sample is a sample time, t convert is a conversion time and TC_Clock_Period is a period of the clock signal.

13. The circuit of claim 11 , where the first and second digital converters are analog-to-digital converters.

14. The circuit of claim 10 , where the event distribution circuit further comprises:
a selection circuit having an input coupled to an output of the event system, the selection circuit configured for outputting first and second logic values in response to the event signal;
a first logic coupled to the selection circuit output and the first digital converter, the first logic configured to start converting the first analog signal to the first digital signal in response to the first logic value; and
a second logic coupled to the selection circuit output and the second digital converter, the second logic configured to start converting the second analog signal to the second digital signal in response to the second logic value.

15. The circuit of claim 14 , where the selection circuit is a counter.

16. The circuit if claim 15 , where the counter is a 1-bit counter.

17. The circuit of claim 14 ,

Assignees

• Atmel Corp

Inventors

• Pedersen Frode Milch
• Birsan Laurentiu
• Igier Frederic

Classifications

• H03M1/121

  Interleaved, i.e. using multiple converters or converter parts for one channel · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/1215 Primary

  using time-division multiplexing · CPC title