Semiconductor element and manufacturing method and operating method of the same

Patent metadata

Field	Value
Publication number	US-9349830-B2
Application number	US-201313784886-A
Country	US
Kind code	B2
Filing date	Mar 5, 2013
Priority date	Mar 5, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.

First claim

What is claimed is:

1. A semiconductor element, comprising:
a substrate;
a first well disposed on the substrate;
a first heavily doping region disposed in the first well;
at least a second heavily doping region disposed in the first heavily doping region;
a gate layer disposed on the first well;
a third heavily doping region disposed on the substrate;
a fourth heavily doping region disposed in the first well;
a second well disposed in the third heavily doping region extending toward the substrate, wherein the second well has the first type doping; and
a third well disposed between the substrate and the third heavily doping region, wherein the third well has the first type doping, and the second well is extending into the third well;
wherein the first heavily doping region, the third heavily doping region, and the fourth heavily doping regions having a first type doping are separated from one another, and the first well and the second heavily doping region have a second type doping complementary to the first type doping.

2. The semiconductor element according to claim 1 , further comprising a plurality of contacts electrically connecting the first heavily doping region and the second heavily doping region to a source terminal.

3. The semiconductor element according to claim 1 , wherein the second well comprise a first region and a second region separated from each other.

4. The semiconductor element according to claim 3 , further comprising a fifth heavily doping region disposed in the third heavily doping region and between the first region and the second region, wherein the fifth heavily doping region has the second type doping.

5. The semiconductor element according to claim 1 , further comprising a first lightly doing region disposed between the first well and the fourth heavily doping region, wherein the first lightly doping region has the first type doping.

6. The semiconductor element according to claim 1 , further comprising:
a field oxide layer disposed between the first well and the third heavily doping region; and
a gate oxide layer, comprising:
a first gate oxide segment disposed between the gate layer and the first well; and
a second gate oxide segment disposed between the first gate oxide segment and the field oxide layer;
wherein a thickness of the first gate oxide segment is smaller than a thickness of the second gate oxide segment.

7. A manufacturing method of a semiconductor element, comprising:
providing a substrate;
forming a first well on the substrate;
forming a first heavily doping region in the first well;
forming at least a second heavily doping region in the first heavily doping region;
forming a gate layer on the first well;
forming a third heavily doping region on the substrate;
forming a fourth heavily doping region in the first well;
forming a second well in the third heavily doping region extending to the substrate, wherein the second well has the first type doping; and
forming a third well between the substrate and the third heavily doping region, wherein the third well has the first type doping, and the second well is extending into the third well;
wherein the first heavily doping region, the third heavily doping region, and the fourth heavily doping regions having a first type doping are separated from one another, and the first well and the second heavily doping region have a second type doping complementary to the first type doping.

8. The manufacturing method of the semiconductor element according to claim 7 , further comprising:
forming a plurality of contacts for electrically connecting the first heavily doping region and the second heavily doping region to a source terminal.

9. The manufacturing method of the semiconductor element according to claim 7 , wherein the second well comprises a first region and a second region separated from each other.

10. The manufacturing method of the semiconductor element according to claim 9 , further comprising:
forming at least a fifth heavily doping region in the third heavily doping region and between the first region and the second region, wherein the fifth region has the second type doping.

11. The manufacturing method of the semiconductor element according to claim 7 , further comprising:
forming a first lightly doping region between the first well and the fourth heavily doping region, wherein the first lightly doping region has the first type doping.

12. The manufacturing method of the semiconductor element according to claim 7 , further comprising:
forming a field oxide layer between the first well and the third heavily doping region; and
forming a gate oxide layer, comprising:
forming a first gate oxide segment between the gate layer and the first well; and
forming a second gate oxide segment between the first gate oxide segment and the field oxide layer;
wherein a thickness of the first gate oxide segment is smaller than a thickness of the second gate oxide segment.

Assignees

• Macronix Int Co Ltd

Inventors

• Chan Wing-Chor
• Chen Hsin-Liang

Classifications

• H10D8/00

  Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00) · CPC title

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D89/813

  specially adapted to provide an electrical current path other than the field-effect induced current path · CPC title

• H10D64/516

  the thicknesses being non-uniform · CPC title

• H10D62/157

  Impurity concentrations or distributions · CPC title