Field plate configuration of a semiconductor device

Patent metadata

Field	Value
Publication number	US-9349811-B2
Application number	US-201213619565-A
Country	US
Kind code	B2
Filing date	Sep 14, 2012
Priority date	Dec 26, 2011
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A semiconductor device includes a semiconductor substrate having a principal surface, and an insulating film formed on the principal surface and continuously covering a top surface of a first boundary region and a top surface of a second boundary region, the first boundary region including a boundary between a well layer and a RESURF layer, the second boundary region including a boundary between the RESURF layer and a first impurity region. The semiconductor device further includes a plurality of lower field plates formed in the insulating film in such a manner that the plurality of lower field plates do not lie directly above the first and second boundary regions, and a plurality of upper field plates formed on the insulating film in such a manner that the plurality of upper field plates do not lie directly above the first and second boundary regions.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a principal surface;
a first impurity region of a first conductivity type formed in said semiconductor substrate;
a RESURF layer of a second conductivity type formed in said semiconductor substrate along said principal surface;
a well layer of said second conductivity type formed in said semiconductor substrate adjacent said RESURF layer and along said principal surface;
a channel stopper of said first conductivity type formed in said semiconductor substrate adjacent said RESURF layer and along said principal surface, with said first impurity region interposed between said channel stopper and said RESURF layer;
an insulating film formed on said principal surface and continuously covering a top surface of a first boundary region and a top surface of a second boundary region, said first boundary region including a first boundary between said well layer and said RESURF layer, said second boundary region including a second boundary between said RESURF layer and said first impurity region and facing said channel stopper;
a plurality of lower field plates formed in said insulating film in such a manner that no lower field plate lies directly above said first boundary and no lower field plate lies directly above said second boundary;
an emitter electrode formed in contact with said well layer and extending over a top surface, opposite the principal surface, of said insulating film directly above said first boundary; and
a channel stopper electrode formed in contact with said channel stopper and extending over a top surface, opposite the principal surface, of said insulating film directly above said second boundary, wherein the channel stopper electrode is not in direct contact with any lower field plate.

2. The semiconductor device according to claim 1 ,
wherein said emitter electrode overlaps a portion of said lower field plate, and said channel stopper electrode overlaps a portion of said lower field plate.

3. The semiconductor device according to claim 2 , further comprising a plurality of upper field plates formed on said insulating film in such a manner that said plurality of upper field plates do not lie directly above said first and second boundary regions;
wherein a first capacitance formed between a first lower plate among said lower plates and said emitter electrode and a second capacitance formed between a second lower plate among said lower plates and said channel stopper electrode are greater than a third capacitance formed between one of said lower plates and one of said upper plates, said first lower plate being the closest of said lower plates to said first boundary region, said second lower plate being the closest of said lower plates to said second boundary region.

4. The semiconductor device according to claim 1 , wherein said RESURF layer is formed of a plurality of regions of said second conductivity type.

5. The semiconductor device according to claim 1 , wherein said RESURF layer is formed to have an impurity concentration of said second conductivity type which gradually decreases away from said well layer toward said channel stopper.

6. The semiconductor device according to claim 1 , wherein a concentration gradient reducing section is formed in the portion of said well layer adjacent said RESURF layer in such a manner that the impurity concentration gradient of said second conductivity type between said well layer and said RESURF layer is reduced.

7. The semiconductor device according to claim 1 , wherein said semiconductor substrate is formed of a wide bandgap semiconductor.

8. The semiconductor device according to claim 7 , wherein said wide bandgap semiconductor is silicon carbide, gallium nitride-based material, or diamond.

9. The semiconductor device according to claim 1 , wherein the insulating film is formed such that there is no direct or electrical contact between any of the lower field plates and at least one of the emitter electrode and the channel stopper electrode.

10. The semiconductor device according to claim 9 , wherein the insulating film is formed such that there is no direct or electrical contact between any of the lower field plates and either of the emitter electrode and the channel stopper electrode.

Assignees

• Takahashi Tetsuo
• Mitsubishi Electric Corp

Inventors

• Takahashi Tetsuo

Classifications

• H10P32/1406

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• H10P32/171

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• H10D62/142

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• H10D62/105

  by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  (IGFETs having LDD or drain extension regions H10D30/601) · CPC title