Aspect ratio trapping and lattice engineering for III/V semiconductors

Patent metadata

Field	Value
Publication number	US-9349809-B1
Application number	US-201414541179-A
Country	US
Kind code	B1
Filing date	Nov 14, 2014
Priority date	Nov 14, 2014
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A method of forming a semiconductor structure. The method may include; forming a hardmask on a strained semiconductor, the strained semiconductor is on a substrate; relaxing edges of the strained semiconductor by forming first trenches through the hardmask and through the strained semiconductor; forming barrier layers in the first trenches; forming a second trench between adjacent barrier layers; and growing a second semiconductor layer on the strained semiconductor having relaxed edges.

First claim

What is claimed is:

1. A method comprising:
forming a silicon-germanium (SiGe) layer on a semiconductor-on-insulator (SOI) layer, the SOI layer is on an insulator layer;
oxidizing the SiGe layer using a Ge-condensation process, such that germanium atoms are displaced from the SiGe layer into the SOI layer and the SiGe layer becomes an oxidized semiconductor layer, the SOI layer having the displaced germanium atoms is a strained SiGe layer;
removing the oxidized semiconductor layer from above the strained SiGe layer;
forming first trenches through a hardmask and into the strained SiGe layer, the hardmask is directly on the strained SiGe layer, edges of the strained SiGe layer are exposed by the first trenches, the edges of the strained SiGe layer are relaxed;
forming barrier layers in the first trenches;
forming a second trench by removing the hardmask; and
growing a III/V semiconductor layer in the second trench, the III/V semiconductor layer is grown on the strained SiGe layer having relaxed edges.

2. The method of claim 1 , wherein the first trenches extend from a top surface of the hardmask to a top surface of the insulator layer.

3. The method of claim 1 , wherein the first trenches create a free surface of the strained SiGe layer on two adjacent vertical sides.

4. The method of claim 1 , wherein the second trench has a trench depth greater-than-or-equal-to double a trench width.

5. The method of claim 1 , wherein the strained SiGe layer having relaxed edges has a lattice constant between a relaxed silicon lattice constant and a relaxed silicon-germanium lattice constant.

6. The method of claim 1 , wherein the barrier layers include an oxide.

7. The method of claim 1 , wherein the SOI layer includes silicon.

8. A method comprising:
forming a hardmask on a strained semiconductor, the strained semiconductor is on a substrate;
relaxing edges of the strained semiconductor by forming first trenches through the hardmask and through the strained semiconductor;
forming barrier layers in the first trenches;
forming a second trench between adjacent barrier layers; and
growing a second semiconductor layer on the strained semiconductor having relaxed edges.

9. The method of claim 8 , wherein the first trenches extend from a top surface of the hardmask to a bottom surface of the strained semiconductor.

10. The method of claim 8 , wherein the first trenches create free surfaces of the strained semiconductor layer on two adjacent vertical sides.

11. The method of claim 8 , wherein the second semiconductor layer is a III/V semiconductor material.

12. The method of claim 8 , wherein the strained semiconductor is SiGe.

13. The method of claim 8 , wherein the barrier layer is an oxide.

14. The method of claim 8 , wherein the strained semiconductor having relaxed edges has a lattice constant between the lattice constant of relaxed silicon and the lattice constant of relaxed silicon-germanium.

15. The method of claim 8 , wherein the strained semiconductor is formed using a Ge-condensation process.

16. The method of claim 8 , wherein the second trench is formed by removing the hardmask.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Hashemi Pouya
• Khakifirooz Ali
• Reznicek Alexander

Classifications

• H10P14/6516

  of treatments performed after formation of the materials · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title