Semiconductor device with face-to-face chips on interposer and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9349711-B2
Application number	US-201514689655-A
Country	US
Kind code	B2
Filing date	Apr 17, 2015
Priority date	Oct 25, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A method of making a semiconductor device with face-to-face chips on interposer includes the step of attaching a chip-on-interposer subassembly on a heat spreader with the chip inserted into a cavity of the heat spreader so that the heat spreader provides mechanical support for the interposer. The heat spreader also provides thermal dissipation, electromagnetic shielding and moisture barrier for the enclosed chip. In the method, a second chip is also electrically coupled to a second surface of the interposer and an optional second heat spreader is attached to the second chip.

First claim

What is claimed is:

1. A semiconductor device with face-to-face chips on interposer, comprising:
a first chip;
a second chip;
an alignment guide;
a first heat spreader having a cavity; and
an interposer having a first surface, a second surface opposite to the first surface, first contact pads on the first surface, second contact pads on the second surface, and through vias that electrically couple the first contact pads and the second contact pads,
wherein the first chip is electrically coupled to the first contact pads of the interposer by a plurality of bumps to provide a chip-on-interposer subassembly;
the chip-on-interposer subassembly is attached to the first heat spreader using a thermally conductive material with the first chip enclosed in the cavity and the interposer laterally extending beyond the cavity;
the second chip is electrically coupled to the second contact pads of the interposer by a plurality of bumps; and
the alignment guide is positioned beyond the cavity of the first heat spreader and laterally aligned with and in close proximity to peripheral edges of the interposer; or the alignment guide is positioned within the cavity of the first heat spreader and laterally aligned with and in close proximity to peripheral edges of the first chip.

2. The semiconductor device of claim 1 , further comprising a balancing layer that covers sidewalls of the interposer.

3. The semiconductor device of claim 2 , further comprising an interconnect substrate that has a through opening and is electrically coupled to additional second contact pads on the second surface of the interposer by a plurality of solder balls with the second chip inserted into the through opening.

4. The semiconductor device of claim 1 , further comprising a second heat spreader that is attached on the second chip.

5. The semiconductor a device of claim 2 , further comprising a second heat spreader that has a cavity and is attached to the second chip using a thermally conductive material with the second chip inserted into the cavity of the second heat spreader and the interposer laterally extending beyond the cavity of the second heat spreader, wherein the interposer laterally extends beyond peripheral edges of the first heat spreader to expose additional first contact pads on the first surface of the interposer.

6. The semiconductor device of claim 5 , further comprising an interconnect substrate that has a through opening and is electrically coupled to the additional first contact pads of the interposer by a plurality of solder balls with the first heat spreader inserted into the through opening.

7. The semiconductor device of claim 2 , further comprising a second heat spreader that has a cavity and is attached to the second chip using a thermally conductive material with the second chip inserted into the cavity of the second heat spreader and the interposer laterally extending beyond the cavity of the second heat spreader, wherein the interposer laterally extends beyond peripheral edges of the second heat spreader to expose additional second contact pads on the second surface of the interposer.

8. The semiconductor device of claim 7 , further comprising an interconnect substrate that has a through opening and is electrically coupled to the additional second contact pads of the interposer by a plurality of solder balls with the second heat spreader inserted into the through opening.

9. A semiconductor device with face-to-face chips on interposer, comprising:
a first chip;
a second chip;
a first heat spreader having a cavity;
an interposer having a first surface, a second surface opposite to the first surface, first contact pads on the first surface, second contact pads on the second surface, and through vias that electrically couple the first contact pads and the second contact pads; and
a second heat spreader that has a cavity,
wherein the first chip is electrically coupled to the first contact pads of the interposer by a plurality of bumps to provide a chip-on-interposer subassembly;
the chip-on-interposer subassembly is attached to the first heat spreader using a thermally conductive material with the first chip enclosed in the cavity and the interposer laterally extending beyond the cavity;
the second chip is electrically coupled to the second contact pads of the interposer by a plurality of bumps;
the second heat spreader is attached to the second chip using a thermally conductive material with the second chip inserted into the cavity of the second heat spreader and the interposer laterally extending beyond the cavity of the second heat spreader; and
the interposer laterally extends beyond peripheral edges of the first heat spreader to expose additional first contact pads on the first surface of the interposer.

10. The semiconductor device of claim 9 , further comprising an interconnect substrate that has a through opening and is electrically coupled to the additional first contact pads of the interposer by a plurality of solder balls with the first heat spreader inserted into the through opening.

11. The semiconductor device of claim 9 , further comprising a balancing layer that covers sidewalls of the interposer.

12. The semiconductor device of claim 11 , further comprising an interconnect substrate that has a through opening and is electrically coupled to the additional first contact pads of the interposer by a plurality of solder balls with the first heat spreader inserted into the through opening.

13. A semiconductor device with face-to-face chips on interposer, comprising:
a first chip;
a second chip;
a first heat spreader having a cavity;
an interposer having a first surface, a second surface opposite to the first surface, first contact pads on the first surface, second contact pads on the second surface, and through vias that electrically couple the first contact pads and the second contact pads; and
an interconnect substrate that has a through opening,
wherein the first chip is electrically coupled to the first contact pads of the interposer by a plurality of bumps to provide a chip-on-interposer subassembly;
the chip-on-interposer subassembly is attached to the first heat spreader using a thermally conductive material with the first chip enclosed in the cavity and the interposer laterally extending beyond the cavity;
the second chip is electrically coupled to the second contact pads of the interposer by a plurality of bumps; and
the interconnect substrate is electrically coupled to additional second contact pads on the second surface of the interposer by a plurality of solder balls with the second chip inserted into the through opening.

14. The semiconductor device of claim 13 , further comprising a balancing layer that covers sidewalls of the interposer.

Assignees

• Bridge Semiconductor Corp

Inventors

• Lin Charles W C
• Wang Chia-Chung

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title